Lines Matching refs:out_be32

29 			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
30 			out_be32(&ddr->cs0_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
33 			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
34 			out_be32(&ddr->cs1_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
37 			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
38 			out_be32(&ddr->cs2_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
41 			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
42 			out_be32(&ddr->cs3_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
46 	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);  in fsl_ddr_set_memctl_regs()
47 	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);  in fsl_ddr_set_memctl_regs()
48 	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);  in fsl_ddr_set_memctl_regs()
49 	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);  in fsl_ddr_set_memctl_regs()
51 	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);  in fsl_ddr_set_memctl_regs()
61 	out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);  in fsl_ddr_set_memctl_regs()