Lines Matching refs:j
243 unsigned int i, j; in __step_assign_addresses() local
261 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { in __step_assign_addresses()
263 if (!pinfo->dimm_params[i][j].n_ranks) in __step_assign_addresses()
265 dw = pinfo->dimm_params[i][j].primary_sdram_width; in __step_assign_addresses()
278 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { in __step_assign_addresses()
280 dw = pinfo->dimm_params[i][j].data_width; in __step_assign_addresses()
281 if (pinfo->dimm_params[i][j].n_ranks in __step_assign_addresses()
366 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { in __step_assign_addresses()
368 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; in __step_assign_addresses()
369 pinfo->dimm_params[i][j].base_address = in __step_assign_addresses()
371 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); in __step_assign_addresses()
390 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { in __step_assign_addresses()
393 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; in __step_assign_addresses()
394 pinfo->dimm_params[i][j].base_address = in __step_assign_addresses()
396 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); in __step_assign_addresses()
420 unsigned int i, j; in fsl_ddr_compute() local
456 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { in fsl_ddr_compute()
458 &(pinfo->spd_installed_dimms[i][j]); in fsl_ddr_compute()
460 &(pinfo->dimm_params[i][j]); in fsl_ddr_compute()
462 i, spd, pdimm, j); in fsl_ddr_compute()
464 if (!j && retval) { in fsl_ddr_compute()
469 i, j); in fsl_ddr_compute()
475 "for memctl=%u dimm=%u\n", i, j); in fsl_ddr_compute()
482 "dimm=%u\n", i, j); in fsl_ddr_compute()
503 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { in fsl_ddr_compute()
505 &(pinfo->dimm_params[i][j]); in fsl_ddr_compute()
506 fsl_ddr_get_dimm_params(pdimm, i, j); in fsl_ddr_compute()
598 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) { in fsl_ddr_compute()
600 if (reg->cs[j].config & 0x80000000) { in fsl_ddr_compute()
606 if (reg->cs[j].bnds == 0xffffffff) in fsl_ddr_compute()
608 end = reg->cs[j].bnds & 0xffff; in fsl_ddr_compute()