ddr/fsl/main.c

45 #if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
46 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
49 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
50 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
54 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
55 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
59 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
60 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
66 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
67 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
72 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
73 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
261 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {  in __step_assign_addresses()
278 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {  in __step_assign_addresses()
366 				for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {  in __step_assign_addresses()
390 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {  in __step_assign_addresses()
456 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {  in fsl_ddr_compute()
503 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {  in fsl_ddr_compute()
523 				 CONFIG_DIMM_SLOTS_PER_CTLR);  in fsl_ddr_compute()
812 	info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;  in fsl_ddr_sdram()
860 	info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;  in fsl_ddr_sdram_size()