52 	unsigned int i, bus_width;  in fsl_ddr_set_memctl_regs()  local
103 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {  in fsl_ddr_set_memctl_regs()
104 		if (i == 0) {  in fsl_ddr_set_memctl_regs()
105 			ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
106 			ddr_out32(&ddr->cs0_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
107 			ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);  in fsl_ddr_set_memctl_regs()
109 		} else if (i == 1) {  in fsl_ddr_set_memctl_regs()
110 			ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
111 			ddr_out32(&ddr->cs1_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
112 			ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);  in fsl_ddr_set_memctl_regs()
114 		} else if (i == 2) {  in fsl_ddr_set_memctl_regs()
115 			ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
116 			ddr_out32(&ddr->cs2_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
117 			ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);  in fsl_ddr_set_memctl_regs()
119 		} else if (i == 3) {  in fsl_ddr_set_memctl_regs()
120 			ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
121 			ddr_out32(&ddr->cs3_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
122 			ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);  in fsl_ddr_set_memctl_regs()
220 	for (i = 0; i < 64; i++) {  in fsl_ddr_set_memctl_regs()
221 		if (regs->debug[i]) {  in fsl_ddr_set_memctl_regs()
223 			      i+1, regs->debug[i]);  in fsl_ddr_set_memctl_regs()
224 			ddr_out32(&ddr->debug[i], regs->debug[i]);  in fsl_ddr_set_memctl_regs()
341 		for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {  in fsl_ddr_set_memctl_regs()
342 			if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))  in fsl_ddr_set_memctl_regs()
347 				 MD_CNTL_CS_SEL(i)			|  in fsl_ddr_set_memctl_regs()
389 			for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {  in fsl_ddr_set_memctl_regs()
390 				if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))  in fsl_ddr_set_memctl_regs()
394 							MD_CNTL_CS_SEL(i) |  in fsl_ddr_set_memctl_regs()
410 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {  in fsl_ddr_set_memctl_regs()
411 		if (!(regs->cs[i].config & 0x80000000))  in fsl_ddr_set_memctl_regs()
414 			((regs->cs[i].config >> 14) & 0x3) + 2 +  in fsl_ddr_set_memctl_regs()
415 			((regs->cs[i].config >> 8) & 0x7) + 12 +  in fsl_ddr_set_memctl_regs()
416 			((regs->cs[i].config >> 4) & 0x3) + 0 +  in fsl_ddr_set_memctl_regs()
417 			((regs->cs[i].config >> 0) & 0x7) + 8 +  in fsl_ddr_set_memctl_regs()