144 	param->write_correct_mask = (1 << rwcfg->mem_dq_per_write_dqs) - 1;  in phy_mgr_initialize()
313 	scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,  in scc_mgr_set_dqs_io_in_delay()
320 		    rwcfg->mem_dq_per_write_dqs + 1 + dm,  in scc_mgr_set_dm_in_delay()
331 	scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,  in scc_mgr_set_dqs_out1_delay()
338 		    rwcfg->mem_dq_per_write_dqs + 1 + dm,  in scc_mgr_set_dm_out1_delay()
584 		for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {  in scc_mgr_zero_group()
644 	for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {  in scc_mgr_apply_group_dq_out1_delay()
686 	for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++)  in scc_mgr_apply_group_all_out_delay_add()
1179 	const u32 shift_ratio = rwcfg->mem_dq_per_write_dqs /  in rw_mgr_mem_calibrate_write_test()
1986 	const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :  in search_stop_check()
2041 	const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :  in search_left_edge()
2152 	const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :  in search_right_edge()
2179 				for (i = 0; i < rwcfg->mem_dq_per_write_dqs;  in search_right_edge()
2270 	const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :  in get_window_mid_index()
2321 	const s32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :  in center_dq_windows()
2954 	int left_edge[rwcfg->mem_dq_per_write_dqs];  in rw_mgr_mem_calibrate_writes_center()
2955 	int right_edge[rwcfg->mem_dq_per_write_dqs];  in rw_mgr_mem_calibrate_writes_center()
2974 			  (rwcfg->mem_dq_per_write_dqs << 2));  in rw_mgr_mem_calibrate_writes_center()
2983 	for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {  in rw_mgr_mem_calibrate_writes_center()
3366 			write_test_bgn += rwcfg->mem_dq_per_write_dqs) {  in mem_calibrate()
3750 		   rwcfg->mem_dq_per_read_dqs, rwcfg->mem_dq_per_write_dqs,  in sdram_calibration_full()