141 	int src_clk;  in rv1126b_peri_set_clk()  local
146 			src_clk = ACLK_PERI_SEL_200M;  in rv1126b_peri_set_clk()
148 			src_clk = ACLK_PERI_SEL_24M;  in rv1126b_peri_set_clk()
151 			     src_clk << ACLK_PERI_SEL_SHIFT);  in rv1126b_peri_set_clk()
155 			src_clk = PCLK_PERI_SEL_100M;  in rv1126b_peri_set_clk()
157 			src_clk = PCLK_PERI_SEL_24M;  in rv1126b_peri_set_clk()
160 			     src_clk << PCLK_PERI_SEL_SHIFT);  in rv1126b_peri_set_clk()
164 			src_clk = ACLK_TOP_SEL_600M;  in rv1126b_peri_set_clk()
166 			src_clk = ACLK_TOP_SEL_400M;  in rv1126b_peri_set_clk()
168 			src_clk = ACLK_TOP_SEL_200M;  in rv1126b_peri_set_clk()
171 			     src_clk << ACLK_TOP_SEL_SHIFT);  in rv1126b_peri_set_clk()
179 			src_clk = ACLK_BUS_SEL_400M;  in rv1126b_peri_set_clk()
181 			src_clk = ACLK_BUS_SEL_300M;  in rv1126b_peri_set_clk()
183 			src_clk = ACLK_BUS_SEL_200M;  in rv1126b_peri_set_clk()
186 			     src_clk << ACLK_BUS_SEL_SHIFT);  in rv1126b_peri_set_clk()
190 			src_clk = HCLK_BUS_SEL_200M;  in rv1126b_peri_set_clk()
192 			src_clk = HCLK_BUS_SEL_100M;  in rv1126b_peri_set_clk()
195 			     src_clk << HCLK_BUS_SEL_SHIFT);  in rv1126b_peri_set_clk()
246 	int src_clk;  in rv1126b_i2c_set_clk()  local
256 			src_clk = CLK_I2C_SEL_24M;  in rv1126b_i2c_set_clk()
258 			src_clk = CLK_I2C_SEL_200M;  in rv1126b_i2c_set_clk()
260 			     src_clk << CLK_I2C_SEL_SHIFT);  in rv1126b_i2c_set_clk()
264 			src_clk = CLK_I2C2_SEL_24M;  in rv1126b_i2c_set_clk()
266 			src_clk = CLK_I2C2_SEL_RCOSC;  in rv1126b_i2c_set_clk()
268 			src_clk = CLK_I2C2_SEL_100M;  in rv1126b_i2c_set_clk()
270 			     src_clk << CLK_I2C2_SEL_SHIFT);  in rv1126b_i2c_set_clk()
555 	int src_clk;  in rv1126b_spi_set_clk()  local
558 		src_clk = CLK_SPI0_SEL_200M;  in rv1126b_spi_set_clk()
560 		src_clk = CLK_SPI0_SEL_100M;  in rv1126b_spi_set_clk()
562 		src_clk = CLK_SPI0_SEL_50M;  in rv1126b_spi_set_clk()
564 		src_clk = CLK_SPI0_SEL_24M;  in rv1126b_spi_set_clk()
569 			     src_clk << CLK_SPI0_SEL_SHIFT);  in rv1126b_spi_set_clk()
573 			     src_clk << CLK_SPI1_SEL_SHIFT);  in rv1126b_spi_set_clk()
629 	int src_clk, src_clk_div, prate;  in rv1126b_pwm_set_clk()  local
632 		src_clk = CLK_PWM_SEL_100M;  in rv1126b_pwm_set_clk()
634 		src_clk = CLK_PWM_SEL_24M;  in rv1126b_pwm_set_clk()
640 			     src_clk << CLK_PWM0_SEL_SHIFT);  in rv1126b_pwm_set_clk()
645 			     src_clk << CLK_PWM2_SEL_SHIFT);  in rv1126b_pwm_set_clk()
650 			     src_clk << CLK_PWM3_SEL_SHIFT);  in rv1126b_pwm_set_clk()
654 			src_clk = CLK_PWM1_SEL_24M;  in rv1126b_pwm_set_clk()
657 			src_clk = CLK_PWM1_SEL_100M;  in rv1126b_pwm_set_clk()
660 			src_clk = CLK_PWM1_SEL_RCOSC;  in rv1126b_pwm_set_clk()
667 			     (src_clk << CLK_PWM1_SEL_SHIFT) |  in rv1126b_pwm_set_clk()
1348 	int src_clk, div, p_rate;  in rv1126b_vop_set_rate()  local
1351 		src_clk = DCLK_VOP_SEL_CPLL;  in rv1126b_vop_set_rate()
1354 		src_clk = DCLK_VOP_SEL_GPLL;  in rv1126b_vop_set_rate()
1362 			     (src_clk << DCLK_VOP_SEL_SHIFT) |  in rv1126b_vop_set_rate()
1418 	int src_clk, div, p_rate;  in rv1126b_mac_set_rate()  local
1424 			src_clk = CLK_GMAC_PTP_REF_SRC_SEL_CPLL;  in rv1126b_mac_set_rate()
1427 			src_clk = CLK_GMAC_PTP_REF_SRC_SEL_24M;  in rv1126b_mac_set_rate()
1434 			     (src_clk << CLK_GMAC_PTP_REF_SRC_SEL_SHIFT) |  in rv1126b_mac_set_rate()
1439 			src_clk = CLK_MAC_OUT2IO_SEL_CPLL;  in rv1126b_mac_set_rate()
1442 			src_clk = CLK_MAC_OUT2IO_SEL_GPLL;  in rv1126b_mac_set_rate()
1445 			src_clk = CLK_MAC_OUT2IO_SEL_24M;  in rv1126b_mac_set_rate()
1451 			     (src_clk << CLK_MAC_OUT2IO_SEL_SHIFT) |  in rv1126b_mac_set_rate()