Lines Matching refs:ret
1601 ulong ret = 0; in rv1126b_clk_set_rate() local
1610 ret = rockchip_pll_set_rate(&rv1126b_pll_clks[GPLL], priv->cru, in rv1126b_clk_set_rate()
1614 ret = rockchip_pll_set_rate(&rv1126b_pll_clks[AUPLL], priv->cru, in rv1126b_clk_set_rate()
1618 ret = rockchip_pll_set_rate(&rv1126b_pll_clks[CPLL], priv->cru, in rv1126b_clk_set_rate()
1629 ret = rv1126b_peri_set_clk(priv, clk->id, rate); in rv1126b_clk_set_rate()
1637 ret = rv1126b_crypto_set_clk(priv, clk->id, rate); in rv1126b_clk_set_rate()
1651 ret = rv1126b_mmc_set_clk(priv, clk->id, rate); in rv1126b_clk_set_rate()
1660 ret = rv1126b_i2c_set_clk(priv, clk->id, rate); in rv1126b_clk_set_rate()
1664 ret = rv1126b_spi_set_clk(priv, clk->id, rate); in rv1126b_clk_set_rate()
1670 ret = rv1126b_pwm_set_clk(priv, clk->id, rate); in rv1126b_clk_set_rate()
1680 ret = rv1126b_adc_set_clk(priv, clk->id, rate); in rv1126b_clk_set_rate()
1689 ret = rv1126b_frac_set_rate(priv, clk->id, rate); in rv1126b_clk_set_rate()
1700 ret = rv1126b_uart_set_rate(priv, clk->id, rate); in rv1126b_clk_set_rate()
1709 ret = rv1126b_wdt_set_rate(priv, clk->id, rate); in rv1126b_clk_set_rate()
1712 ret = rv1126b_vop_set_rate(priv, clk->id, rate); in rv1126b_clk_set_rate()
1719 ret = rv1126b_mac_set_rate(priv, clk->id, rate); in rv1126b_clk_set_rate()
1726 return ret; in rv1126b_clk_set_rate()
1741 ulong ret = 0; in rv1126b_clk_enable() local
1746 ret = writel(BITS_WITH_WMASK(0, 0x1U, 13), in rv1126b_clk_enable()
1750 ret = writel(BITS_WITH_WMASK(0, 0x1U, 9), in rv1126b_clk_enable()
1754 ret = writel(BITS_WITH_WMASK(0, 0x1U, 8), in rv1126b_clk_enable()
1758 ret = writel(BITS_WITH_WMASK(0, 0x1U, 14), in rv1126b_clk_enable()
1762 ret = writel(BITS_WITH_WMASK(0, 0x1U, 13), in rv1126b_clk_enable()
1766 ret = writel(BITS_WITH_WMASK(0, 0x1U, 12), in rv1126b_clk_enable()
1771 return ret; in rv1126b_clk_enable()
1773 return ret; in rv1126b_clk_enable()
1778 ulong ret = 0; in rv1126b_clk_disable() local
1783 ret = writel(BITS_WITH_WMASK(1, 0x1U, 13), in rv1126b_clk_disable()
1787 ret = writel(BITS_WITH_WMASK(1, 0x1U, 9), in rv1126b_clk_disable()
1791 ret = writel(BITS_WITH_WMASK(1, 0x1U, 8), in rv1126b_clk_disable()
1795 ret = writel(BITS_WITH_WMASK(1, 0x1U, 14), in rv1126b_clk_disable()
1799 ret = writel(BITS_WITH_WMASK(1, 0x1U, 13), in rv1126b_clk_disable()
1803 ret = writel(BITS_WITH_WMASK(1, 0x1U, 12), in rv1126b_clk_disable()
1808 return ret; in rv1126b_clk_disable()
1810 return ret; in rv1126b_clk_disable()
1825 int ret; in rv1126b_clk_init() local
1831 ret = rockchip_pll_set_rate(&rv1126b_pll_clks[GPLL], priv->cru, in rv1126b_clk_init()
1833 if (!ret) in rv1126b_clk_init()
1839 ret = rockchip_pll_set_rate(&rv1126b_pll_clks[AUPLL], priv->cru, in rv1126b_clk_init()
1841 if (!ret) in rv1126b_clk_init()
1847 ret = rockchip_pll_set_rate(&rv1126b_pll_clks[CPLL], priv->cru, in rv1126b_clk_init()
1849 if (!ret) in rv1126b_clk_init()
1857 int ret; in rv1126b_clk_probe() local
1881 ret = clk_set_defaults(dev); in rv1126b_clk_probe()
1882 if (ret) in rv1126b_clk_probe()
1883 debug("%s clk_set_defaults failed %d\n", __func__, ret); in rv1126b_clk_probe()
1900 int ret; in rv1126b_clk_bind() local
1906 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", in rv1126b_clk_bind()
1908 if (ret) { in rv1126b_clk_bind()
1909 debug("Warning: No sysreset driver: ret=%d\n", ret); in rv1126b_clk_bind()
1919 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", in rv1126b_clk_bind()
1921 if (ret) { in rv1126b_clk_bind()
1922 debug("Warning: No rockchip reset driver: ret=%d\n", ret); in rv1126b_clk_bind()
1965 int i, ret; in soc_clk_dump() local
1967 ret = uclass_get_device_by_driver(UCLASS_CLK, in soc_clk_dump()
1970 if (ret) { in soc_clk_dump()
1972 return ret; in soc_clk_dump()
1987 ret = clk_request(cru_dev, &clk); in soc_clk_dump()
1988 if (ret < 0) in soc_clk_dump()
1989 return ret; in soc_clk_dump()