Lines Matching full:else
87 else if (sel == ACLK_PERI_SEL_200M) in rv1106_peri_get_clk()
89 else if (sel == ACLK_PERI_SEL_100M) in rv1106_peri_get_clk()
91 else in rv1106_peri_get_clk()
99 else if (sel == HCLK_PERI_SEL_100M) in rv1106_peri_get_clk()
101 else if (sel == HCLK_PERI_SEL_50M) in rv1106_peri_get_clk()
103 else in rv1106_peri_get_clk()
111 else if (sel == PCLK_PERI_SEL_50M) in rv1106_peri_get_clk()
113 else in rv1106_peri_get_clk()
121 else if (sel == ACLK_BUS_SEL_200M) in rv1106_peri_get_clk()
123 else if (sel == ACLK_BUS_SEL_100M) in rv1106_peri_get_clk()
125 else in rv1106_peri_get_clk()
133 else if (sel == PCLK_TOP_SEL_50M) in rv1106_peri_get_clk()
135 else in rv1106_peri_get_clk()
143 else in rv1106_peri_get_clk()
151 else if (sel == HCLK_PMU_SEL_100M) in rv1106_peri_get_clk()
153 else in rv1106_peri_get_clk()
173 else if (rate >= 198 * MHz) in rv1106_peri_set_clk()
175 else if (rate >= 99 * MHz) in rv1106_peri_set_clk()
177 else in rv1106_peri_set_clk()
186 else if (rate >= 99 * MHz) in rv1106_peri_set_clk()
188 else if (rate >= 48 * MHz) in rv1106_peri_set_clk()
190 else in rv1106_peri_set_clk()
199 else if (rate >= 48 * MHz) in rv1106_peri_set_clk()
201 else in rv1106_peri_set_clk()
210 else if (rate >= 198 * MHz) in rv1106_peri_set_clk()
212 else if (rate >= 99 * MHz) in rv1106_peri_set_clk()
214 else in rv1106_peri_set_clk()
223 else if (rate >= 48 * MHz) in rv1106_peri_set_clk()
225 else in rv1106_peri_set_clk()
234 else in rv1106_peri_set_clk()
243 else if (rate >= 99 * MHz) in rv1106_peri_set_clk()
245 else in rv1106_peri_set_clk()
271 else if (sel == CLK_I2C1_SEL_100M) in rv1106_i2c_get_clk()
273 else if (sel == CLK_I2C1_SEL_24M) in rv1106_i2c_get_clk()
275 else in rv1106_i2c_get_clk()
300 else if (sel == CLK_I2C0_SEL_100M) in rv1106_i2c_get_clk()
302 else if (sel == CLK_I2C0_SEL_50M) in rv1106_i2c_get_clk()
304 else in rv1106_i2c_get_clk()
352 else if (rate >= 198 * MHz) in rv1106_crypto_set_clk()
354 else if (rate >= 99 * MHz) in rv1106_crypto_set_clk()
356 else in rv1106_crypto_set_clk()
391 else in rv1106_mmc_get_clk()
403 else in rv1106_mmc_get_clk()
415 else if (sel == CLK_SFC_SEL_300M) in rv1106_mmc_get_clk()
417 else if (sel == CLK_SFC_SEL_200M) in rv1106_mmc_get_clk()
419 else in rv1106_mmc_get_clk()
437 } else { in rv1106_mmc_set_clk()
449 } else { in rv1106_mmc_set_clk()
466 } else { in rv1106_mmc_set_clk()
483 } else if ((500 * MHz % rate) == 0) { in rv1106_mmc_set_clk()
486 } else if ((300 * MHz % rate) == 0) { in rv1106_mmc_set_clk()
489 } else { in rv1106_mmc_set_clk()
516 else if (rate >= 99 * MHz) in rv1106_i2c_set_clk()
518 else if (rate >= 48 * MHz) in rv1106_i2c_set_clk()
520 else in rv1106_i2c_set_clk()
527 else if (rate >= 99 * MHz) in rv1106_i2c_set_clk()
529 else if (rate >= 24 * MHz) in rv1106_i2c_set_clk()
531 else in rv1106_i2c_set_clk()
579 else if (sel == CLK_SPI0_SEL_100M) in rv1106_spi_get_clk()
581 else if (sel == CLK_SPI0_SEL_50M) in rv1106_spi_get_clk()
583 else in rv1106_spi_get_clk()
597 else if (rate >= 99 * MHz) in rv1106_spi_set_clk()
599 else if (rate >= 48 * MHz) in rv1106_spi_set_clk()
601 else in rv1106_spi_set_clk()
663 else if (rate >= 48 * MHz) in rv1106_pwm_set_clk()
665 else in rv1106_pwm_set_clk()
840 else if (p_src == CLK_UART_SRC_SEL_CPLL) in rv1106_uart_get_rate()
842 else in rv1106_uart_get_rate()
846 } else if (src == CLK_UART_SEL_FRAC) { in rv1106_uart_get_rate()
853 } else { in rv1106_uart_get_rate()
869 } else if (priv->cpll_hz % rate == 0) { in rv1106_uart_set_rate()
873 } else if (rate == OSC_HZ) { in rv1106_uart_set_rate()
877 } else { in rv1106_uart_set_rate()
937 else if (sel == ACLK_VOP_SEL_200M) in rv1106_vop_get_clk()
939 else if (sel == ACLK_VOP_SEL_100M) in rv1106_vop_get_clk()
941 else in rv1106_vop_get_clk()
950 else in rv1106_vop_get_clk()
968 else if (rate >= 198 * MHz) in rv1106_vop_set_clk()
970 else if (rate >= 99 * MHz) in rv1106_vop_set_clk()
972 else in rv1106_vop_set_clk()
983 } else { in rv1106_vop_set_clk()
1010 else if (sel == DCLK_DECOM_SEL_200M) in rv1106_decom_get_clk()
1012 else if (sel == DCLK_DECOM_SEL_100M) in rv1106_decom_get_clk()
1014 else in rv1106_decom_get_clk()
1026 else if (rate >= 198 * MHz) in rv1106_decom_set_clk()
1028 else if (rate >= 99 * MHz) in rv1106_decom_set_clk()
1030 else in rv1106_decom_set_clk()
1308 else in rv1106_clk_probe()
1310 #else in rv1106_clk_probe()
1346 } else { in rv1106_clk_bind()
1359 } else { in rv1106_clk_bind()
1444 else if (clk->id == SCLK_SDMMC_SAMPLE) in rv1106_mmc_get_phase()
1446 else if (clk->id == SCLK_SDIO_SAMPLE) in rv1106_mmc_get_phase()
1497 else if (clk->id == SCLK_SDMMC_SAMPLE) in rv1106_mmc_set_phase()
1499 else if (clk->id == SCLK_SDIO_SAMPLE) in rv1106_mmc_set_phase()
1633 else in soc_clk_dump()
1636 } else { in soc_clk_dump()
1640 else in soc_clk_dump()