95 	ulong plliclk, v;  in pic32_get_pll_rate()  local
97 	v = readl(priv->iobase + SPLLCON);  in pic32_get_pll_rate()
98 	iclk = (v & ICLK_MASK);  in pic32_get_pll_rate()
99 	idiv = ((v >> 8) & PLLIDIV_MASK) + 1;  in pic32_get_pll_rate()
100 	odiv = ((v >> 24) & PLLODIV_MASK);  in pic32_get_pll_rate()
101 	mult = ((v >> 16) & PLLMUL_MASK) + 1;  in pic32_get_pll_rate()
117 	ulong v;  in pic32_get_sysclk()  local
123 	v = readl(priv->iobase + OSCCON);  in pic32_get_sysclk()
124 	curr_osc = (v >> 12) & CUROSC_MASK;  in pic32_get_sysclk()
128 		frcdiv = ((v >> 24) & FRCDIV_MASK);  in pic32_get_sysclk()
174 	u32 div, trim, v;  in pic32_set_refclk()  local
204 	v = readl(reg);  in pic32_set_refclk()
205 	v &= ~(REFO_SEL_MASK << REFO_SEL_SHIFT);  in pic32_set_refclk()
206 	v |= (parent_id << REFO_SEL_SHIFT);  in pic32_set_refclk()
209 	v &= ~(REFO_DIV_MASK << REFO_DIV_SHIFT);  in pic32_set_refclk()
210 	v |= (div << REFO_DIV_SHIFT);  in pic32_set_refclk()
211 	writel(v, reg);  in pic32_set_refclk()
214 	v = readl(reg + REFO_TRIM_REG);  in pic32_set_refclk()
215 	v &= ~(REFO_TRIM_MASK << REFO_TRIM_SHIFT);  in pic32_set_refclk()
216 	v |= (trim << REFO_TRIM_SHIFT);  in pic32_set_refclk()
217 	writel(v, reg + REFO_TRIM_REG);  in pic32_set_refclk()
232 	u32 rodiv, rotrim, rosel, v, parent_rate;  in pic32_get_refclk()  local
239 	v = readl(reg);  in pic32_get_refclk()
241 	rosel = (v >> REFO_SEL_SHIFT) & REFO_SEL_MASK;  in pic32_get_refclk()
243 	rodiv = (v >> REFO_DIV_SHIFT) & REFO_DIV_MASK;  in pic32_get_refclk()
246 	v = readl(reg + REFO_TRIM_REG);  in pic32_get_refclk()
247 	rotrim = (v >> REFO_TRIM_SHIFT) & REFO_TRIM_MASK;  in pic32_get_refclk()
274 		v = (u32)rate64;  in pic32_get_refclk()
276 		v = parent_rate / (rodiv << 1);  in pic32_get_refclk()
278 	return v;  in pic32_get_refclk()
283 	u32 v, idiv, mul;  in pic32_get_mpll_rate()  local
287 	v = readl(priv->syscfg_base + CFGMPLL);  in pic32_get_mpll_rate()
288 	idiv = v & MPLL_IDIV;  in pic32_get_mpll_rate()
289 	mul = (v >> MPLL_MULT_SHIFT) & MPLL_MULT;  in pic32_get_mpll_rate()
290 	odiv1 = (v >> MPLL_ODIV1_SHIFT) & MPLL_ODIV1;  in pic32_get_mpll_rate()
291 	odiv2 = (v >> MPLL_ODIV2_SHIFT) & MPLL_ODIV2;  in pic32_get_mpll_rate()
302 	u32 v, mask;  in pic32_mpll_init()  local
305 	v = (MPLL_IDIV_INIT << MPLL_IDIV_SHIFT) |  in pic32_mpll_init()
310 	writel(v, priv->syscfg_base + CFGMPLL);  in pic32_mpll_init()