116 	void __iomem *port_mmio = uc_priv->port[port].port_mmio;  in ahci_link_up()  local
122 	writel(0x4, port_mmio + PORT_SCR_CTL);  in ahci_link_up()
124 	writel(0x1, port_mmio + PORT_SCR_CTL);  in ahci_link_up()
126 	writel(0x0, port_mmio + PORT_SCR_CTL);  in ahci_link_up()
129 	writel(0x301, port_mmio + PORT_SCR_CTL);  in ahci_link_up()
131 	writel(0x300, port_mmio + PORT_SCR_CTL);  in ahci_link_up()
140 		tmp = readl(port_mmio + PORT_SCR_STAT);  in ahci_link_up()
152 static void sunxi_dma_init(void __iomem *port_mmio)  in sunxi_dma_init()  argument
154 	clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);  in sunxi_dma_init()
200 	void __iomem *port_mmio;  in ahci_host_init()  local
250 		uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);  in ahci_host_init()
253 		port_mmio = (u8 *)uc_priv->port[i].port_mmio;  in ahci_host_init()
256 		tmp = readl(port_mmio + PORT_CMD);  in ahci_host_init()
262 			writel_with_flush(tmp, port_mmio + PORT_CMD);  in ahci_host_init()
271 		sunxi_dma_init(port_mmio);  in ahci_host_init()
277 		cmd = readl(port_mmio + PORT_CMD);  in ahci_host_init()
279 		writel_with_flush(cmd, port_mmio + PORT_CMD);  in ahci_host_init()
291 		tmp = readl(port_mmio + PORT_SCR_ERR);  in ahci_host_init()
293 			writel(tmp, port_mmio + PORT_SCR_ERR);  in ahci_host_init()
299 			tmp = readl(port_mmio + PORT_TFDATA);  in ahci_host_init()
303 			tmp = readl(port_mmio + PORT_SCR_STAT);  in ahci_host_init()
310 		tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;  in ahci_host_init()
323 		tmp = readl(port_mmio + PORT_SCR_ERR);  in ahci_host_init()
325 		writel(tmp, port_mmio + PORT_SCR_ERR);  in ahci_host_init()
328 		tmp = readl(port_mmio + PORT_IRQ_STAT);  in ahci_host_init()
331 			writel(tmp, port_mmio + PORT_IRQ_STAT);  in ahci_host_init()
336 		tmp = readl(port_mmio + PORT_SCR_STAT);  in ahci_host_init()
560 static int wait_spinup(void __iomem *port_mmio)  in wait_spinup()  argument
567 		tf_data = readl(port_mmio + PORT_TFDATA);  in wait_spinup()
578 	void __iomem *port_mmio = pp->port_mmio;  in ahci_port_start()  local
584 	port_status = readl(port_mmio + PORT_SCR_STAT);  in ahci_port_start()
626 	writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);  in ahci_port_start()
627 	writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);  in ahci_port_start()
629 	writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);  in ahci_port_start()
630 	writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);  in ahci_port_start()
633 	sunxi_dma_init(port_mmio);  in ahci_port_start()
638 			  PORT_CMD_START, port_mmio + PORT_CMD);  in ahci_port_start()
646 	return wait_spinup(port_mmio);  in ahci_port_start()
655 	void __iomem *port_mmio = pp->port_mmio;  in ahci_device_data_io()  local
667 	port_status = readl(port_mmio + PORT_SCR_STAT);  in ahci_device_data_io()
682 	writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);  in ahci_device_data_io()
684 	if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,  in ahci_device_data_io()
1134 	void __iomem *port_mmio = pp->port_mmio;  in ata_io_flush()  local
1146 	writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);  in ata_io_flush()
1148 	if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,  in ata_io_flush()