197 	void __iomem *mmio = uc_priv->mmio_base;  in ahci_host_init()  local
205 	cap_save = readl(mmio + HOST_CAP);  in ahci_host_init()
213 	writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);  in ahci_host_init()
214 	writel(cap_save, mmio + HOST_CAP);  in ahci_host_init()
215 	writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);  in ahci_host_init()
236 	uc_priv->cap = readl(mmio + HOST_CAP);  in ahci_host_init()
237 	uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);  in ahci_host_init()
250 		uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);  in ahci_host_init()
333 		writel(1 << i, mmio + HOST_IRQ_STAT);  in ahci_host_init()
342 	tmp = readl(mmio + HOST_CTL);  in ahci_host_init()
344 	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);  in ahci_host_init()
345 	tmp = readl(mmio + HOST_CTL);  in ahci_host_init()
374 	void __iomem *mmio = uc_priv->mmio_base;  in ahci_print_info()  local
379 	vers = readl(mmio + HOST_VERSION);  in ahci_print_info()
381 	cap2 = readl(mmio + HOST_CAP2);  in ahci_print_info()