390 	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,  in clock_init()
395 	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,  in clock_init()
397 	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,  in clock_init()
401 	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,  in clock_init()
403 	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,  in clock_init()
406 	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,  in clock_init()
408 	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,  in clock_init()
410 	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,  in clock_init()
412 	clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,  in clock_init()
419 	clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS |  in clock_init()
423 	clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS |  in clock_init()
429 	clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |  in clock_init()
434 		clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |  in clock_init()
440 	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,  in clock_init()
443 	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,  in clock_init()
455 	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |  in clock_init()
463 	clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,  in clock_init()
466 	clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,  in clock_init()
469 	clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,  in clock_init()
471 	clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,  in clock_init()
474 	clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,  in clock_init()
476 	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,  in clock_init()