Lines Matching refs:usdhc_cfg
364 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { variable
395 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
396 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in board_mmc_init()
397 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
399 usdhc_cfg[0].max_bus_width = 8; in board_mmc_init()
400 usdhc_cfg[1].max_bus_width = 8; in board_mmc_init()
401 usdhc_cfg[2].max_bus_width = 4; in board_mmc_init()
423 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); in board_mmc_init()
443 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; in board_mmc_init()
444 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in board_mmc_init()
445 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
450 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; in board_mmc_init()
451 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
452 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
457 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; in board_mmc_init()
458 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
459 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
465 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); in board_mmc_init()