73 static struct nand_bd *bd;	/* DMA buffer descriptors	*/  variable
110 	writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);  in axs101_nand_write_buf()
111 	writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);  in axs101_nand_write_buf()
112 	writel(bbstate.bounce_buffer, &bd->buffer_ptr0);  in axs101_nand_write_buf()
113 	writel(0, &bd->buffer_ptr1);  in axs101_nand_write_buf()
116 	flush_dcache_range((unsigned long)bd,  in axs101_nand_write_buf()
117 			   (unsigned long)bd + sizeof(struct nand_bd));  in axs101_nand_write_buf()
144 	writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);  in axs101_nand_read_buf()
145 	writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);  in axs101_nand_read_buf()
146 	writel(bbstate.bounce_buffer, &bd->buffer_ptr0);  in axs101_nand_read_buf()
147 	writel(0, &bd->buffer_ptr1);  in axs101_nand_read_buf()
150 	flush_dcache_range((unsigned long)bd,  in axs101_nand_read_buf()
151 			   (unsigned long)bd + sizeof(struct nand_bd));  in axs101_nand_read_buf()
225 	bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN,  in board_nand_init()
229 	NAND_REG_WRITE(IDMAC_BDADDR, bd);  in board_nand_init()