Lines Matching +full:- +full:k
5 * SPDX-License-Identifier: GPL-2.0+
28 #include "../common/ioep-fpga.h"
73 res = mclink_send(fpga - 1, regoff, data); in fpga_set_reg()
95 return -EINVAL; in fpga_get_reg()
96 res = mclink_receive(fpga - 1, regoff, data); in fpga_get_reg()
129 unsigned int k; in last_stage_init() local
151 for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) { in last_stage_init()
156 if (i2c_probe(mclink_controllers[k])) { in last_stage_init()
158 if (i2c_probe(mclink_controllers[k])) in last_stage_init()
162 if (i2c_probe(mclink_controllers[k])) in last_stage_init()
165 while (!(pca953x_get_val(mclink_controllers[k]) in last_stage_init()
169 printf("no done for mclink_controller %d\n", k); in last_stage_init()
174 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); in last_stage_init()
175 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); in last_stage_init()
177 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, in last_stage_init()
185 return -ENOMEM; in last_stage_init()
186 strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); in last_stage_init()
187 mdiodev->read = bb_miiphy_read; in last_stage_init()
188 mdiodev->write = bb_miiphy_write; in last_stage_init()
201 /* give slave-PLLs and Parade DP501 some time to be up and running */ in last_stage_init()
238 for (k = 1; k <= slaves; ++k) in last_stage_init()
239 FPGA_SET_REG(k, extended_control, 0x10); /* enable video */ in last_stage_init()
244 for (k = 1; k <= slaves; ++k) { in last_stage_init()
245 ioep_fpga_print_info(k); in last_stage_init()
247 if (ioep_fpga_has_osd(k)) in last_stage_init()
248 osd_probe(k); in last_stage_init()
251 if (ioep_fpga_has_osd(k)) { in last_stage_init()
252 osd_probe(k); in last_stage_init()
254 osd_probe(k + 4); in last_stage_init()
258 if (!adv7611_probe(k)) in last_stage_init()
260 ch7301_probe(k, false); in last_stage_init()
261 dp501_probe(k, false); in last_stage_init()
267 return -ENOMEM; in last_stage_init()
268 strncpy(mdiodev->name, bb_miiphy_buses[k].name, in last_stage_init()
270 mdiodev->read = bb_miiphy_read; in last_stage_init()
271 mdiodev->write = bb_miiphy_write; in last_stage_init()
276 setup_88e1514(bb_miiphy_buses[k].name, 0); in last_stage_init()
280 for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) { in last_stage_init()
281 i2c_set_bus_num(strider_fans[k].bus); in last_stage_init()
282 init_fan_controller(strider_fans[k].addr); in last_stage_init()
344 * set "startup-finished"-gpios in mpc8308_setup_hw()
346 setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); in mpc8308_setup_hw()
347 setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); in mpc8308_setup_hw()
359 sysconf83xx_t *sysconf = &immr->sysconf; in board_mmc_init()
362 out_be32(&sysconf->sdhccr, 0x02000000); in board_mmc_init()
386 sysconf83xx_t *sysconf = &immr->sysconf; in pci_init_board()
387 law83xx_t *pcie_law = sysconf->pcielaw; in pci_init_board()
394 out_be32(&sysconf->pecr1, 0xE0008000); in pci_init_board()
406 info->portwidth = FLASH_CFI_16BIT; in board_flash_get_legacy()
407 info->chipwidth = FLASH_CFI_BY16; in board_flash_get_legacy()
408 info->interface = FLASH_CFI_X16; in board_flash_get_legacy()
444 struct fpga_mii *fpga_mii = bus->priv; in mii_mdio_active()
446 if (fpga_mii->mdio) in mii_mdio_active()
447 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_active()
449 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); in mii_mdio_active()
456 struct fpga_mii *fpga_mii = bus->priv; in mii_mdio_tristate()
458 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_tristate()
465 struct fpga_mii *fpga_mii = bus->priv; in mii_set_mdio()
468 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_set_mdio()
470 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); in mii_set_mdio()
472 fpga_mii->mdio = v; in mii_set_mdio()
480 struct fpga_mii *fpga_mii = bus->priv; in mii_get_mdio()
482 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); in mii_get_mdio()
491 struct fpga_mii *fpga_mii = bus->priv; in mii_set_mdc()
494 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); in mii_set_mdc()
496 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); in mii_set_mdc()