Lines Matching +full:- +full:k
5 * SPDX-License-Identifier: GPL-2.0+
25 #include "../common/ioep-fpga.h"
70 res = mclink_send(fpga - 1, regoff, data); in fpga_set_reg()
92 return -EINVAL; in fpga_get_reg()
93 res = mclink_receive(fpga - 1, regoff, data); in fpga_get_reg()
126 unsigned int k; in last_stage_init() local
142 for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { in last_stage_init()
145 if (i2c_probe(mclink_controllers[k])) in last_stage_init()
148 while (!(pca953x_get_val(mclink_controllers[k]) in last_stage_init()
152 printf("no done for mclink_controller %d\n", k); in last_stage_init()
157 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); in last_stage_init()
158 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); in last_stage_init()
160 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, in last_stage_init()
168 return -ENOMEM; in last_stage_init()
169 strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); in last_stage_init()
170 mdiodev->read = bb_miiphy_read; in last_stage_init()
171 mdiodev->write = bb_miiphy_write; in last_stage_init()
184 /* give slave-PLLs and Parade DP501 some time to be up and running */ in last_stage_init()
202 for (k = 1; k <= slaves; ++k) { in last_stage_init()
203 FPGA_GET_REG(k, fpga_features, &fpga_features); in last_stage_init()
205 ioep_fpga_print_info(k); in last_stage_init()
206 osd_probe(k); in last_stage_init()
208 osd_probe(k + 4); in last_stage_init()
214 return -ENOMEM; in last_stage_init()
215 strncpy(mdiodev->name, bb_miiphy_buses[k].name, in last_stage_init()
217 mdiodev->read = bb_miiphy_read; in last_stage_init()
218 mdiodev->write = bb_miiphy_write; in last_stage_init()
223 setup_88e1514(bb_miiphy_buses[k].name, 0); in last_stage_init()
227 for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) { in last_stage_init()
228 i2c_set_bus_num(hrcon_fans[k].bus); in last_stage_init()
229 init_fan_controller(hrcon_fans[k].addr); in last_stage_init()
241 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin); in fpga_gpio_set()
246 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin); in fpga_gpio_clear()
253 FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val); in fpga_gpio_get()
262 FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val); in fpga_control_set()
263 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin); in fpga_control_set()
270 FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val); in fpga_control_clear()
271 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin); in fpga_control_clear()
289 * set "startup-finished"-gpios in mpc8308_setup_hw()
291 setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); in mpc8308_setup_hw()
292 setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); in mpc8308_setup_hw()
304 sysconf83xx_t *sysconf = &immr->sysconf; in board_mmc_init()
307 out_be32(&sysconf->sdhccr, 0x02000000); in board_mmc_init()
331 sysconf83xx_t *sysconf = &immr->sysconf; in pci_init_board()
332 law83xx_t *pcie_law = sysconf->pcielaw; in pci_init_board()
339 out_be32(&sysconf->pecr1, 0xE0008000); in pci_init_board()
351 info->portwidth = FLASH_CFI_16BIT; in board_flash_get_legacy()
352 info->chipwidth = FLASH_CFI_BY16; in board_flash_get_legacy()
353 info->interface = FLASH_CFI_X16; in board_flash_get_legacy()
389 struct fpga_mii *fpga_mii = bus->priv; in mii_mdio_active()
391 if (fpga_mii->mdio) in mii_mdio_active()
392 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_active()
394 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); in mii_mdio_active()
401 struct fpga_mii *fpga_mii = bus->priv; in mii_mdio_tristate()
403 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_tristate()
410 struct fpga_mii *fpga_mii = bus->priv; in mii_set_mdio()
413 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_set_mdio()
415 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); in mii_set_mdio()
417 fpga_mii->mdio = v; in mii_set_mdio()
425 struct fpga_mii *fpga_mii = bus->priv; in mii_get_mdio()
427 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); in mii_get_mdio()
436 struct fpga_mii *fpga_mii = bus->priv; in mii_set_mdc()
439 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); in mii_set_mdc()
441 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); in mii_set_mdc()