1331 static struct fsl_esdhc_cfg usdhc_cfg[2];  variable
1346 		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;  in board_mmc_init()
1347 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);  in board_mmc_init()
1348 		usdhc_cfg[0].max_bus_width = 4;  in board_mmc_init()
1349 		return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);  in board_mmc_init()
1353 		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;  in board_mmc_init()
1354 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);  in board_mmc_init()
1355 		usdhc_cfg[0].max_bus_width = 8;  in board_mmc_init()
1356 		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);  in board_mmc_init()
1361 		usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;  in board_mmc_init()
1362 		usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);  in board_mmc_init()
1363 		usdhc_cfg[1].max_bus_width = 4;  in board_mmc_init()
1364 		return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);  in board_mmc_init()
1368 		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;  in board_mmc_init()
1369 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);  in board_mmc_init()
1370 		usdhc_cfg[0].max_bus_width = 8;  in board_mmc_init()
1371 		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);  in board_mmc_init()
1376 		usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;  in board_mmc_init()
1377 		usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);  in board_mmc_init()
1378 		usdhc_cfg[1].max_bus_width = 4;  in board_mmc_init()
1379 		return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);  in board_mmc_init()
1383 		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;  in board_mmc_init()
1384 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);  in board_mmc_init()
1385 		usdhc_cfg[0].max_bus_width = 8;  in board_mmc_init()
1386 		return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);  in board_mmc_init()