89 					PAD_CTL_PKE | PAD_CTL_DSE_HIGH));  in board_ehci_hcd_init()
97 					PAD_CTL_PKE | PAD_CTL_DSE_HIGH));  in board_ehci_hcd_init()
113 			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),  in setup_iomux_fec()
114 		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),  in setup_iomux_fec()
123 		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),  in setup_iomux_fec()
128 		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),  in setup_iomux_fec()
129 		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),  in setup_iomux_fec()
142 		NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),  in setup_iomux_fec()
145 		NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),  in setup_iomux_fec()
164 #define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
167 				 PAD_CTL_DSE_HIGH)
220 #define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
277 				PAD_CTL_DSE_HIGH),  in setup_iomux_nand()
279 				PAD_CTL_DSE_HIGH),  in setup_iomux_nand()
281 				PAD_CTL_DSE_HIGH),  in setup_iomux_nand()
283 				PAD_CTL_DSE_HIGH),  in setup_iomux_nand()
289 				PAD_CTL_DSE_HIGH),  in setup_iomux_nand()
291 				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),  in setup_iomux_nand()
293 				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),  in setup_iomux_nand()
295 				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),  in setup_iomux_nand()
297 				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),  in setup_iomux_nand()
299 				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),  in setup_iomux_nand()
301 				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),  in setup_iomux_nand()
303 				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),  in setup_iomux_nand()
305 				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),  in setup_iomux_nand()
319 					    PAD_CTL_DSE_HIGH | PAD_CTL_PKE));  in m53_set_clock()