Lines Matching refs:section

17 ; This section allows setting the PLL0 system clock with a
32 ; This section allows setting up the PLL1. Usually this will
42 ; This section lets us configure the peripheral interface
57 ; This section can be used to configure the PLL1 and the EMIF3a registers
59 ; See PLL1CONFIG section for the format of the PLL1CFG fields.
79 ; This section can be used to configure the EMIFA to use
95 ; This section can be used to configure the async chip selects
117 ; This section should be used in place of PLL0CONFIG when
120 ; See PLL0CONFIG section for the format of the PLL0CFG fields.
121 ; See PERIPHCLKCFG section for the format of the CLKCFG field.
131 ; This section should be used to setup the power state of modules
132 ; of the two PSCs.  This section can be included multiple times to
139 ; This section allows setting of a single PINMUX register.
140 ; This section can be included multiple times to allow setting
151 ; No Params required - simply include this section for the fast boot
155 ; This section allows setting up the PLL1. Usually this will
165 ; This section can be used to configure the PLL1 and the EMIF3a registers
182 ; This section can be used to configure the PLL1 and the EMIF3a registers