Lines Matching refs:XCHAL_DCACHE_LINEWIDTH

18 #define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
85 	__loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
103 	__loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
112 	__loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
122 			 XCHAL_DCACHE_LINEWIDTH
142 	__loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
151 	__loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
160 	__loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
179 	__loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
188 	__loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
197 	__loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH