127 void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane)  in training_message()  argument
130 	DPF(D_INFO, "CH%01X RK%01X BL%01X\n", channel, rank, byte_lane);  in training_message()
139 	      uint8_t byte_lane, uint32_t pi_count)  in set_rcvn()  argument
148 	    channel, rank, byte_lane, pi_count);  in set_rcvn()
155 	reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in set_rcvn()
157 	msk = (byte_lane & 1) ? 0xf00000 : 0xf00;  in set_rcvn()
158 	temp = (byte_lane & 1) ? (pi_count / HALF_CLK) << 20 :  in set_rcvn()
170 	reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;  in set_rcvn()
171 	reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in set_rcvn()
182 	reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in set_rcvn()
188 	msk |= (byte_lane & 1) ? (1 << 5) : (1 << 2);  in set_rcvn()
193 	msk |= (byte_lane & 1) ? (1 << 11) : (1 << 8);  in set_rcvn()
201 		training_message(channel, rank, byte_lane);  in set_rcvn()
214 uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane)  in get_rcvn()  argument
227 	reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in get_rcvn()
230 	temp >>= (byte_lane & 1) ? 20 : 8;  in get_rcvn()
241 	reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;  in get_rcvn()
242 	reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in get_rcvn()
263 	      uint8_t byte_lane, uint32_t pi_count)  in set_rdqs()  argument
271 	    channel, rank, byte_lane, pi_count);  in set_rdqs()
278 	reg = (byte_lane & 1) ? B1RXDQSPICODE : B0RXDQSPICODE;  in set_rdqs()
279 	reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in set_rdqs()
287 		training_message(channel, rank, byte_lane);  in set_rdqs()
300 uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane)  in get_rdqs()  argument
313 	reg = (byte_lane & 1) ? B1RXDQSPICODE : B0RXDQSPICODE;  in get_rdqs()
314 	reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in get_rdqs()
333 	      uint8_t byte_lane, uint32_t pi_count)  in set_wdqs()  argument
342 	    channel, rank, byte_lane, pi_count);  in set_wdqs()
349 	reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in set_wdqs()
351 	msk = (byte_lane & 1) ? 0xf0000 : 0xf0;  in set_wdqs()
353 	temp <<= (byte_lane & 1) ? 16 : 4;  in set_wdqs()
364 	reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;  in set_wdqs()
365 	reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in set_wdqs()
376 	reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in set_wdqs()
382 	msk |= (byte_lane & 1) ? (1 << 4) : (1 << 1);  in set_wdqs()
387 	msk |= (byte_lane & 1) ? (1 << 10) : (1 << 7);  in set_wdqs()
395 		training_message(channel, rank, byte_lane);  in set_wdqs()
408 uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane)  in get_wdqs()  argument
421 	reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in get_wdqs()
424 	temp >>= (byte_lane & 1) ? 16 : 4;  in get_wdqs()
435 	reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;  in get_wdqs()
436 	reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in get_wdqs()
457 	     uint8_t byte_lane, uint32_t pi_count)  in set_wdq()  argument
466 	    channel, rank, byte_lane, pi_count);  in set_wdq()
473 	reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in set_wdq()
475 	msk = (byte_lane & 1) ? 0xf000 : 0xf;  in set_wdq()
477 	temp <<= (byte_lane & 1) ? 12 : 0;  in set_wdq()
488 	reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;  in set_wdq()
489 	reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in set_wdq()
500 	reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in set_wdq()
506 	msk |= (byte_lane & 1) ? (1 << 3) : (1 << 0);  in set_wdq()
511 	msk |= (byte_lane & 1) ? (1 << 9) : (1 << 6);  in set_wdq()
519 		training_message(channel, rank, byte_lane);  in set_wdq()
532 uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane)  in get_wdq()  argument
545 	reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in get_wdq()
548 	temp >>= (byte_lane & 1) ? 12 : 0;  in get_wdq()
559 	reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;  in get_wdq()
560 	reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +  in get_wdq()
937 void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting)  in set_vref()  argument
939 	uint32_t reg = (byte_lane & 0x1) ? B1VREFCTL : B0VREFCTL;  in set_vref()
944 	    channel, byte_lane, setting);  in set_vref()
947 		(byte_lane >> 1) * DDRIODQ_BL_OFFSET,  in set_vref()
965 uint32_t get_vref(uint8_t channel, uint8_t byte_lane)  in get_vref()  argument
969 	uint32_t reg = (byte_lane & 0x1) ? B1VREFCTL : B0VREFCTL;  in get_vref()
975 		(byte_lane >> 1) * DDRIODQ_BL_OFFSET);  in get_vref()