Lines Matching defs:ccsr_tsec
284 typedef struct ccsr_tsec { struct
285 uint id; /* 0x24000 - Controller ID Register */
286 char res1[12];
287 uint ievent; /* 0x24010 - Interrupt Event Register */
288 uint imask; /* 0x24014 - Interrupt Mask Register */
289 uint edis; /* 0x24018 - Error Disabled Register */
290 char res2[4];
291 uint ecntrl; /* 0x24020 - Ethernet Control Register */
292 char res2_1[4];
293 uint ptv; /* 0x24028 - Pause Time Value Register */
294 uint dmactrl; /* 0x2402c - DMA Control Register */
295 uint tbipa; /* 0x24030 - TBI PHY Address Register */
296 char res3[88];
297 uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
298 char res4[8];
299 uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
300 uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */
301 char res4_1[4];
302 uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */
303 uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */
304 char res5[84];
305 uint tctrl; /* 0x24100 - Transmit Control Register */
306 uint tstat; /* 0x24104 - Transmit Status Register */
307 uint dfvlan; /* 0x24108 - Default VLAN control word */
308 char res6[4];
309 uint txic; /* 0x24110 - Transmit interrupt coalescing Register */
310 uint tqueue; /* 0x24114 - Transmit Queue Control Register */
311 char res7[40];
312 uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
313 uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
314 char res8[52];
315 uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */
316 char res9[4];
317 uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
318 char res10[4];
319 uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
320 char res11[4];
321 uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
322 char res12[4];
323 uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
324 char res13[4];
325 uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
326 char res14[4];
327 uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
328 char res15[4];
329 uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
330 char res16[4];
331 uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
332 char res17[64];
333 uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
334 uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */
335 char res18[4];
336 uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */
337 char res19[4];
338 uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */
339 char res20[4];
340 uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */
341 char res21[4];
342 uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */
343 char res22[4];
344 uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */
345 char res23[4];
346 uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */
347 char res24[4];
348 uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */
349 char res25[192];
350 uint rctrl; /* 0x24300 - Receive Control Register */
351 uint rstat; /* 0x24304 - Receive Status Register */
352 char res26[8];
353 uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */
354 uint rqueue; /* 0x24314 - Receive queue control register */
355 char res27[24];
356 uint rbifx; /* 0x24330 - Receive bit field extract control Register */
357 uint rqfar; /* 0x24334 - Receive queue filing table address Register */
358 uint rqfcr; /* 0x24338 - Receive queue filing table control Register */
359 uint rqfpr; /* 0x2433c - Receive queue filing table property Register */
360 uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
361 char res28[56];
362 uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */
363 char res29[4];
364 uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
365 char res30[4];
366 uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
367 char res31[4];
368 uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
369 char res32[4];
370 uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
371 char res33[4];
372 uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
373 char res34[4];
374 uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
375 char res35[4];
376 uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
377 char res36[4];
378 uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
379 char res37[64];
380 uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
381 uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */
382 char res38[4];
383 uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */
384 char res39[4];
385 uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */
386 char res40[4];
387 uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */
388 char res41[4];
389 uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */
390 char res42[4];
391 uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */
392 char res43[4];
393 uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */
394 char res44[4];
395 uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */
396 char res45[192];
397 uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
398 uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
399 uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
400 uint hafdup; /* 0x2450c - Half Duplex Register */
401 uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
402 char res46[12];
403 uint miimcfg; /* 0x24520 - MII Management Configuration Register */
404 uint miimcom; /* 0x24524 - MII Management Command Register */
405 uint miimadd; /* 0x24528 - MII Management Address Register */
406 uint miimcon; /* 0x2452c - MII Management Control Register */
407 uint miimstat; /* 0x24530 - MII Management Status Register */
408 uint miimind; /* 0x24534 - MII Management Indicator Register */
409 uint ifctrl; /* 0x24538 - Interface Contrl Register */
410 uint ifstat; /* 0x2453c - Interface Status Register */
411 uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
412 uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
413 uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */
414 uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */
415 uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */
416 uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */
417 uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */
418 uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */
419 uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */
420 uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */
421 uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */
422 uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */
423 uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */
424 uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */
425 uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */
426 uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */
427 uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */
428 uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */
429 uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */
430 uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */
431 uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */
432 uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */
433 uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */
434 uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */
435 uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */
436 uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */
437 uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */
438 uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */
439 uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */
440 uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */
441 uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */
442 uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */
443 char res48[192];
444 uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
445 uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
446 uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
447 uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
448 uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
449 uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
450 uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
451 uint rbyt; /* 0x2469c - Receive Byte Counter */
452 uint rpkt; /* 0x246a0 - Receive Packet Counter */
453 uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
454 uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
455 uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
456 uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
457 uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
458 uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
459 uint raln; /* 0x246bc - Receive Alignment Error Counter */
460 uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
461 uint rcde; /* 0x246c4 - Receive Code Error Counter */
462 uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
463 uint rund; /* 0x246cc - Receive Undersize Packet Counter */
464 uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
465 uint rfrg; /* 0x246d4 - Receive Fragments Counter */
466 uint rjbr; /* 0x246d8 - Receive Jabber Counter */
467 uint rdrp; /* 0x246dc - Receive Drop Counter */
468 uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
469 uint tpkt; /* 0x246e4 - Transmit Packet Counter */
470 uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
471 uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
472 uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
473 uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
474 uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
475 uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
476 uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
477 uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
478 uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
479 uint tncl; /* 0x2470c - Transmit Total Collision Counter */
480 char res49[4];
481 uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
482 uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
483 uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
484 uint txcf; /* 0x24720 - Transmit Control Frame Counter */
485 uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
486 uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
487 uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
488 uint car1; /* 0x24730 - Carry Register One */
489 uint car2; /* 0x24734 - Carry Register Two */
490 uint cam1; /* 0x24738 - Carry Mask Register One */
491 uint cam2; /* 0x2473c - Carry Mask Register Two */
492 uint rrej; /* 0x24740 - Receive filer rejected packet counter */
493 char res50[188];
517 } ccsr_tsec_t; argument