include/asm/immap_85xx.h

335 typedef struct ccsr_tsec {  struct
336 	u8	res1[16];
337 	u32	ievent;		/* IRQ Event */
338 	u32	imask;		/* IRQ Mask */
339 	u32	edis;		/* Error Disabled */
340 	u8	res2[4];
341 	u32	ecntrl;		/* Ethernet Control */
342 	u32	minflr;		/* Minimum Frame Len */
343 	u32	ptv;		/* Pause Time Value */
344 	u32	dmactrl;	/* DMA Control */
345 	u32	tbipa;		/* TBI PHY Addr */
346 	u8	res3[88];
347 	u32	fifo_tx_thr;		/* FIFO transmit threshold */
348 	u8	res4[8];
349 	u32	fifo_tx_starve;		/* FIFO transmit starve */
350 	u32	fifo_tx_starve_shutoff;	/* FIFO transmit starve shutoff */
351 	u8	res5[96];
352 	u32	tctrl;		/* TX Control */
353 	u32	tstat;		/* TX Status */
354 	u8	res6[4];
355 	u32	tbdlen;		/* TX Buffer Desc Data Len */
356 	u8	res7[16];
357 	u32	ctbptrh;	/* Current TX Buffer Desc Ptr High */
358 	u32	ctbptr;		/* Current TX Buffer Desc Ptr */
359 	u8	res8[88];
360 	u32	tbptrh;		/* TX Buffer Desc Ptr High */
361 	u32	tbptr;		/* TX Buffer Desc Ptr Low */
362 	u8	res9[120];
363 	u32	tbaseh;		/* TX Desc Base Addr High */
364 	u32	tbase;		/* TX Desc Base Addr */
365 	u8	res10[168];
366 	u32	ostbd;		/* Out-of-Sequence(OOS) TX Buffer Desc */
367 	u32	ostbdp;		/* OOS TX Data Buffer Ptr */
368 	u32	os32tbdp;	/* OOS 32 Bytes TX Data Buffer Ptr Low */
369 	u32	os32iptrh;	/* OOS 32 Bytes TX Insert Ptr High */
370 	u32	os32iptrl;	/* OOS 32 Bytes TX Insert Ptr Low */
371 	u32	os32tbdr;	/* OOS 32 Bytes TX Reserved */
372 	u32	os32iil;	/* OOS 32 Bytes TX Insert Idx/Len */
373 	u8	res11[52];
374 	u32	rctrl;		/* RX Control */
375 	u32	rstat;		/* RX Status */
376 	u8	res12[4];
377 	u32	rbdlen;		/* RxBD Data Len */
378 	u8	res13[16];
379 	u32	crbptrh;	/* Current RX Buffer Desc Ptr High */
380 	u32	crbptr;		/* Current RX Buffer Desc Ptr */
381 	u8	res14[24];
382 	u32	mrblr;		/* Maximum RX Buffer Len */
383 	u32	mrblr2r3;	/* Maximum RX Buffer Len R2R3 */
384 	u8	res15[56];
385 	u32	rbptrh;		/* RX Buffer Desc Ptr High 0 */
386 	u32	rbptr;		/* RX Buffer Desc Ptr */
387 	u32	rbptrh1;	/* RX Buffer Desc Ptr High 1 */
388 	u32	rbptrl1;	/* RX Buffer Desc Ptr Low 1 */
389 	u32	rbptrh2;	/* RX Buffer Desc Ptr High 2 */
390 	u32	rbptrl2;	/* RX Buffer Desc Ptr Low 2 */
391 	u32	rbptrh3;	/* RX Buffer Desc Ptr High 3 */
392 	u32	rbptrl3;	/* RX Buffer Desc Ptr Low 3 */
393 	u8	res16[96];
394 	u32	rbaseh;		/* RX Desc Base Addr High 0 */
395 	u32	rbase;		/* RX Desc Base Addr */
396 	u32	rbaseh1;	/* RX Desc Base Addr High 1 */
397 	u32	rbasel1;	/* RX Desc Base Addr Low 1 */
398 	u32	rbaseh2;	/* RX Desc Base Addr High 2 */
399 	u32	rbasel2;	/* RX Desc Base Addr Low 2 */
400 	u32	rbaseh3;	/* RX Desc Base Addr High 3 */
401 	u32	rbasel3;	/* RX Desc Base Addr Low 3 */
402 	u8	res17[224];
403 	u32	maccfg1;	/* MAC Configuration 1 */
404 	u32	maccfg2;	/* MAC Configuration 2 */
405 	u32	ipgifg;		/* Inter Packet Gap/Inter Frame Gap */
406 	u32	hafdup;		/* Half Duplex */
407 	u32	maxfrm;		/* Maximum Frame Len */
408 	u8	res18[12];
409 	u32	miimcfg;	/* MII Management Configuration */
410 	u32	miimcom;	/* MII Management Cmd */
411 	u32	miimadd;	/* MII Management Addr */
412 	u32	miimcon;	/* MII Management Control */
413 	u32	miimstat;	/* MII Management Status */
414 	u32	miimind;	/* MII Management Indicator */
415 	u8	res19[4];
416 	u32	ifstat;		/* Interface Status */
417 	u32	macstnaddr1;	/* Station Addr Part 1 */
418 	u32	macstnaddr2;	/* Station Addr Part 2 */
419 	u8	res20[312];
420 	u32	tr64;		/* TX & RX 64-byte Frame Counter */
421 	u32	tr127;		/* TX & RX 65-127 byte Frame Counter */
422 	u32	tr255;		/* TX & RX 128-255 byte Frame Counter */
423 	u32	tr511;		/* TX & RX 256-511 byte Frame Counter */
424 	u32	tr1k;		/* TX & RX 512-1023 byte Frame Counter */
425 	u32	trmax;		/* TX & RX 1024-1518 byte Frame Counter */
426 	u32	trmgv;		/* TX & RX 1519-1522 byte Good VLAN Frame */
427 	u32	rbyt;		/* RX Byte Counter */
428 	u32	rpkt;		/* RX Packet Counter */
429 	u32	rfcs;		/* RX FCS Error Counter */
430 	u32	rmca;		/* RX Multicast Packet Counter */
431 	u32	rbca;		/* RX Broadcast Packet Counter */
432 	u32	rxcf;		/* RX Control Frame Packet Counter */
433 	u32	rxpf;		/* RX Pause Frame Packet Counter */
434 	u32	rxuo;		/* RX Unknown OP Code Counter */
435 	u32	raln;		/* RX Alignment Error Counter */
436 	u32	rflr;		/* RX Frame Len Error Counter */
437 	u32	rcde;		/* RX Code Error Counter */
438 	u32	rcse;		/* RX Carrier Sense Error Counter */
439 	u32	rund;		/* RX Undersize Packet Counter */
440 	u32	rovr;		/* RX Oversize Packet Counter */
441 	u32	rfrg;		/* RX Fragments Counter */
442 	u32	rjbr;		/* RX Jabber Counter */
443 	u32	rdrp;		/* RX Drop Counter */
444 	u32	tbyt;		/* TX Byte Counter Counter */
445 	u32	tpkt;		/* TX Packet Counter */
446 	u32	tmca;		/* TX Multicast Packet Counter */
447 	u32	tbca;		/* TX Broadcast Packet Counter */
448 	u32	txpf;		/* TX Pause Control Frame Counter */
449 	u32	tdfr;		/* TX Deferral Packet Counter */
450 	u32	tedf;		/* TX Excessive Deferral Packet Counter */
451 	u32	tscl;		/* TX Single Collision Packet Counter */
452 	u32	tmcl;		/* TX Multiple Collision Packet Counter */
453 	u32	tlcl;		/* TX Late Collision Packet Counter */
454 	u32	txcl;		/* TX Excessive Collision Packet Counter */
455 	u32	tncl;		/* TX Total Collision Counter */
456 	u8	res21[4];
457 	u32	tdrp;		/* TX Drop Frame Counter */
458 	u32	tjbr;		/* TX Jabber Frame Counter */
459 	u32	tfcs;		/* TX FCS Error Counter */
460 	u32	txcf;		/* TX Control Frame Counter */
461 	u32	tovr;		/* TX Oversize Frame Counter */
462 	u32	tund;		/* TX Undersize Frame Counter */
463 	u32	tfrg;		/* TX Fragments Frame Counter */
464 	u32	car1;		/* Carry One */
465 	u32	car2;		/* Carry Two */
466 	u32	cam1;		/* Carry Mask One */
467 	u32	cam2;		/* Carry Mask Two */
468 	u8	res22[192];
469 	u32	iaddr0;		/* Indivdual addr 0 */
470 	u32	iaddr1;		/* Indivdual addr 1 */
471 	u32	iaddr2;		/* Indivdual addr 2 */
472 	u32	iaddr3;		/* Indivdual addr 3 */
473 	u32	iaddr4;		/* Indivdual addr 4 */
474 	u32	iaddr5;		/* Indivdual addr 5 */
475 	u32	iaddr6;		/* Indivdual addr 6 */
476 	u32	iaddr7;		/* Indivdual addr 7 */
477 	u8	res23[96];
478 	u32	gaddr0;		/* Global addr 0 */
479 	u32	gaddr1;		/* Global addr 1 */
480 	u32	gaddr2;		/* Global addr 2 */
481 	u32	gaddr3;		/* Global addr 3 */
482 	u32	gaddr4;		/* Global addr 4 */
483 	u32	gaddr5;		/* Global addr 5 */
484 	u32	gaddr6;		/* Global addr 6 */
485 	u32	gaddr7;		/* Global addr 7 */
486 	u8	res24[96];
487 	u32	pmd0;		/* Pattern Match Data */
488 	u8	res25[4];
489 	u32	pmask0;		/* Pattern Mask */
490 	u8	res26[4];
491 	u32	pcntrl0;	/* Pattern Match Control */
492 	u8	res27[4];
493 	u32	pattrb0;	/* Pattern Match Attrs */
494 	u32	pattrbeli0;	/* Pattern Match Attrs Extract Len & Idx */
495 	u32	pmd1;		/* Pattern Match Data */
496 	u8	res28[4];
497 	u32	pmask1;		/* Pattern Mask */
498 	u8	res29[4];
499 	u32	pcntrl1;	/* Pattern Match Control */
500 	u8	res30[4];
501 	u32	pattrb1;	/* Pattern Match Attrs */
502 	u32	pattrbeli1;	/* Pattern Match Attrs Extract Len & Idx */
503 	u32	pmd2;		/* Pattern Match Data */
504 	u8	res31[4];
505 	u32	pmask2;		/* Pattern Mask */
506 	u8	res32[4];
507 	u32	pcntrl2;	/* Pattern Match Control */
508 	u8	res33[4];
509 	u32	pattrb2;	/* Pattern Match Attrs */
510 	u32	pattrbeli2;	/* Pattern Match Attrs Extract Len & Idx */
511 	u32	pmd3;		/* Pattern Match Data */
512 	u8	res34[4];
513 	u32	pmask3;		/* Pattern Mask */
514 	u8	res35[4];
515 	u32	pcntrl3;	/* Pattern Match Control */
516 	u8	res36[4];
517 	u32	pattrb3;	/* Pattern Match Attrs */
518 	u32	pattrbeli3;	/* Pattern Match Attrs Extract Len & Idx */
519 	u32	pmd4;		/* Pattern Match Data */
520 	u8	res37[4];
521 	u32	pmask4;		/* Pattern Mask */
522 	u8	res38[4];
523 	u32	pcntrl4;	/* Pattern Match Control */
524 	u8	res39[4];
525 	u32	pattrb4;	/* Pattern Match Attrs */
526 	u32	pattrbeli4;	/* Pattern Match Attrs Extract Len & Idx */
527 	u32	pmd5;		/* Pattern Match Data */
528 	u8	res40[4];
529 	u32	pmask5;		/* Pattern Mask */
530 	u8	res41[4];
531 	u32	pcntrl5;	/* Pattern Match Control */
532 	u8	res42[4];
533 	u32	pattrb5;	/* Pattern Match Attrs */
534 	u32	pattrbeli5;	/* Pattern Match Attrs Extract Len & Idx */
535 	u32	pmd6;		/* Pattern Match Data */
536 	u8	res43[4];
537 	u32	pmask6;		/* Pattern Mask */
538 	u8	res44[4];
539 	u32	pcntrl6;	/* Pattern Match Control */
540 	u8	res45[4];
541 	u32	pattrb6;	/* Pattern Match Attrs */
542 	u32	pattrbeli6;	/* Pattern Match Attrs Extract Len & Idx */
543 	u32	pmd7;		/* Pattern Match Data */
544 	u8	res46[4];
545 	u32	pmask7;		/* Pattern Mask */
546 	u8	res47[4];
547 	u32	pcntrl7;	/* Pattern Match Control */
548 	u8	res48[4];
549 	u32	pattrb7;	/* Pattern Match Attrs */
550 	u32	pattrbeli7;	/* Pattern Match Attrs Extract Len & Idx */
551 	u32	pmd8;		/* Pattern Match Data */
552 	u8	res49[4];
553 	u32	pmask8;		/* Pattern Mask */
554 	u8	res50[4];
555 	u32	pcntrl8;	/* Pattern Match Control */
556 	u8	res51[4];
557 	u32	pattrb8;	/* Pattern Match Attrs */
558 	u32	pattrbeli8;	/* Pattern Match Attrs Extract Len & Idx */
559 	u32	pmd9;		/* Pattern Match Data */
560 	u8	res52[4];
561 	u32	pmask9;		/* Pattern Mask */
562 	u8	res53[4];
563 	u32	pcntrl9;	/* Pattern Match Control */
564 	u8	res54[4];
565 	u32	pattrb9;	/* Pattern Match Attrs */
566 	u32	pattrbeli9;	/* Pattern Match Attrs Extract Len & Idx */
567 	u32	pmd10;		/* Pattern Match Data */
568 	u8	res55[4];
569 	u32	pmask10;	/* Pattern Mask */
570 	u8	res56[4];
571 	u32	pcntrl10;	/* Pattern Match Control */
572 	u8	res57[4];
573 	u32	pattrb10;	/* Pattern Match Attrs */
574 	u32	pattrbeli10;	/* Pattern Match Attrs Extract Len & Idx */
575 	u32	pmd11;		/* Pattern Match Data */
576 	u8	res58[4];
577 	u32	pmask11;	/* Pattern Mask */
578 	u8	res59[4];
579 	u32	pcntrl11;	/* Pattern Match Control */
580 	u8	res60[4];
581 	u32	pattrb11;	/* Pattern Match Attrs */
582 	u32	pattrbeli11;	/* Pattern Match Attrs Extract Len & Idx */
583 	u32	pmd12;		/* Pattern Match Data */
584 	u8	res61[4];
585 	u32	pmask12;	/* Pattern Mask */
586 	u8	res62[4];
587 	u32	pcntrl12;	/* Pattern Match Control */
588 	u8	res63[4];
589 	u32	pattrb12;	/* Pattern Match Attrs */
590 	u32	pattrbeli12;	/* Pattern Match Attrs Extract Len & Idx */
591 	u32	pmd13;		/* Pattern Match Data */
592 	u8	res64[4];
593 	u32	pmask13;	/* Pattern Mask */
594 	u8	res65[4];
595 	u32	pcntrl13;	/* Pattern Match Control */
619 } ccsr_tsec_t;  argument