Lines Matching defs:ccsr_scfg

3186 struct ccsr_scfg {  struct
3187 	u32 dpslpcr;	/* 0x000 Deep Sleep Control register */
3188 	u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
3189 	u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
3190 	u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
3191 	u32 res1[4];
3192 	u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
3193 	u32 res2;
3194 	u32 pixclkcr;	/* 0x028 Pixel Clock Control register */
3195 	u32 res3[245];
3196 	u32 qeioclkcr;	/* 0x400 QUICC Engine IO Clock Control register */
3197 	u32 emiiocr;	/* 0x404 EMI MDIO Control Register */
3198 	u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */
3199 	u32 qmifrstcr;	/* 0x40c QMAN Interface Reset Control register */
3200 	u32 res4[60];
3201 	u32 sparecr[8];	/* 0x500 Spare Control register(0-7) */