include/asm/immap_85xx.h

622 typedef struct ccsr_pic {  struct
623 	u8	res1[64];
624 	u32	ipidr0;		/* Interprocessor IRQ Dispatch 0 */
625 	u8	res2[12];
626 	u32	ipidr1;		/* Interprocessor IRQ Dispatch 1 */
627 	u8	res3[12];
628 	u32	ipidr2;		/* Interprocessor IRQ Dispatch 2 */
629 	u8	res4[12];
630 	u32	ipidr3;		/* Interprocessor IRQ Dispatch 3 */
631 	u8	res5[12];
632 	u32	ctpr;		/* Current Task Priority */
633 	u8	res6[12];
634 	u32	whoami;		/* Who Am I */
635 	u8	res7[12];
636 	u32	iack;		/* IRQ Acknowledge */
637 	u8	res8[12];
638 	u32	eoi;		/* End Of IRQ */
639 	u8	res9[3916];
640 	u32	frr;		/* Feature Reporting */
641 	u8	res10[28];
642 	u32	gcr;		/* Global Configuration */
645 	u8	res11[92];
646 	u32	vir;		/* Vendor Identification */
647 	u8	res12[12];
648 	u32	pir;		/* Processor Initialization */
649 	u8	res13[12];
650 	u32	ipivpr0;	/* IPI Vector/Priority 0 */
651 	u8	res14[12];
652 	u32	ipivpr1;	/* IPI Vector/Priority 1 */
653 	u8	res15[12];
654 	u32	ipivpr2;	/* IPI Vector/Priority 2 */
655 	u8	res16[12];
656 	u32	ipivpr3;	/* IPI Vector/Priority 3 */
657 	u8	res17[12];
658 	u32	svr;		/* Spurious Vector */
659 	u8	res18[12];
660 	u32	tfrr;		/* Timer Frequency Reporting */
661 	u8	res19[12];
662 	u32	gtccr0;		/* Global Timer Current Count 0 */
663 	u8	res20[12];
664 	u32	gtbcr0;		/* Global Timer Base Count 0 */
665 	u8	res21[12];
666 	u32	gtvpr0;		/* Global Timer Vector/Priority 0 */
667 	u8	res22[12];
668 	u32	gtdr0;		/* Global Timer Destination 0 */
669 	u8	res23[12];
670 	u32	gtccr1;		/* Global Timer Current Count 1 */
671 	u8	res24[12];
672 	u32	gtbcr1;		/* Global Timer Base Count 1 */
673 	u8	res25[12];
674 	u32	gtvpr1;		/* Global Timer Vector/Priority 1 */
675 	u8	res26[12];
676 	u32	gtdr1;		/* Global Timer Destination 1 */
677 	u8	res27[12];
678 	u32	gtccr2;		/* Global Timer Current Count 2 */
679 	u8	res28[12];
680 	u32	gtbcr2;		/* Global Timer Base Count 2 */
681 	u8	res29[12];
682 	u32	gtvpr2;		/* Global Timer Vector/Priority 2 */
683 	u8	res30[12];
684 	u32	gtdr2;		/* Global Timer Destination 2 */
685 	u8	res31[12];
686 	u32	gtccr3;		/* Global Timer Current Count 3 */
687 	u8	res32[12];
688 	u32	gtbcr3;		/* Global Timer Base Count 3 */
689 	u8	res33[12];
690 	u32	gtvpr3;		/* Global Timer Vector/Priority 3 */
691 	u8	res34[12];
692 	u32	gtdr3;		/* Global Timer Destination 3 */
693 	u8	res35[268];
694 	u32	tcr;		/* Timer Control */
695 	u8	res36[12];
696 	u32	irqsr0;		/* IRQ_OUT Summary 0 */
697 	u8	res37[12];
698 	u32	irqsr1;		/* IRQ_OUT Summary 1 */
699 	u8	res38[12];
700 	u32	cisr0;		/* Critical IRQ Summary 0 */
701 	u8	res39[12];
702 	u32	cisr1;		/* Critical IRQ Summary 1 */
703 	u8	res40[188];
704 	u32	msgr0;		/* Message 0 */
705 	u8	res41[12];
706 	u32	msgr1;		/* Message 1 */
707 	u8	res42[12];
708 	u32	msgr2;		/* Message 2 */
709 	u8	res43[12];
710 	u32	msgr3;		/* Message 3 */
711 	u8	res44[204];
712 	u32	mer;		/* Message Enable */
713 	u8	res45[12];
714 	u32	msr;		/* Message Status */
715 	u8	res46[60140];
716 	u32	eivpr0;		/* External IRQ Vector/Priority 0 */
717 	u8	res47[12];
718 	u32	eidr0;		/* External IRQ Destination 0 */
719 	u8	res48[12];
720 	u32	eivpr1;		/* External IRQ Vector/Priority 1 */
721 	u8	res49[12];
722 	u32	eidr1;		/* External IRQ Destination 1 */
723 	u8	res50[12];
724 	u32	eivpr2;		/* External IRQ Vector/Priority 2 */
725 	u8	res51[12];
726 	u32	eidr2;		/* External IRQ Destination 2 */
727 	u8	res52[12];
728 	u32	eivpr3;		/* External IRQ Vector/Priority 3 */
729 	u8	res53[12];
730 	u32	eidr3;		/* External IRQ Destination 3 */
731 	u8	res54[12];
732 	u32	eivpr4;		/* External IRQ Vector/Priority 4 */
733 	u8	res55[12];
734 	u32	eidr4;		/* External IRQ Destination 4 */
735 	u8	res56[12];
736 	u32	eivpr5;		/* External IRQ Vector/Priority 5 */
737 	u8	res57[12];
738 	u32	eidr5;		/* External IRQ Destination 5 */
739 	u8	res58[12];
740 	u32	eivpr6;		/* External IRQ Vector/Priority 6 */
741 	u8	res59[12];
742 	u32	eidr6;		/* External IRQ Destination 6 */
743 	u8	res60[12];
744 	u32	eivpr7;		/* External IRQ Vector/Priority 7 */
745 	u8	res61[12];
746 	u32	eidr7;		/* External IRQ Destination 7 */
747 	u8	res62[12];
748 	u32	eivpr8;		/* External IRQ Vector/Priority 8 */
749 	u8	res63[12];
750 	u32	eidr8;		/* External IRQ Destination 8 */
751 	u8	res64[12];
752 	u32	eivpr9;		/* External IRQ Vector/Priority 9 */
753 	u8	res65[12];
754 	u32	eidr9;		/* External IRQ Destination 9 */
755 	u8	res66[12];
756 	u32	eivpr10;	/* External IRQ Vector/Priority 10 */
757 	u8	res67[12];
758 	u32	eidr10;		/* External IRQ Destination 10 */
759 	u8	res68[12];
760 	u32	eivpr11;	/* External IRQ Vector/Priority 11 */
761 	u8	res69[12];
762 	u32	eidr11;		/* External IRQ Destination 11 */
763 	u8	res70[140];
764 	u32	iivpr0;		/* Internal IRQ Vector/Priority 0 */
765 	u8	res71[12];
766 	u32	iidr0;		/* Internal IRQ Destination 0 */
767 	u8	res72[12];
768 	u32	iivpr1;		/* Internal IRQ Vector/Priority 1 */
769 	u8	res73[12];
770 	u32	iidr1;		/* Internal IRQ Destination 1 */
771 	u8	res74[12];
772 	u32	iivpr2;		/* Internal IRQ Vector/Priority 2 */
773 	u8	res75[12];
774 	u32	iidr2;		/* Internal IRQ Destination 2 */
775 	u8	res76[12];
776 	u32	iivpr3;		/* Internal IRQ Vector/Priority 3 */
777 	u8	res77[12];
778 	u32	iidr3;		/* Internal IRQ Destination 3 */
779 	u8	res78[12];
780 	u32	iivpr4;		/* Internal IRQ Vector/Priority 4 */
781 	u8	res79[12];
782 	u32	iidr4;		/* Internal IRQ Destination 4 */
783 	u8	res80[12];
784 	u32	iivpr5;		/* Internal IRQ Vector/Priority 5 */
785 	u8	res81[12];
786 	u32	iidr5;		/* Internal IRQ Destination 5 */
787 	u8	res82[12];
788 	u32	iivpr6;		/* Internal IRQ Vector/Priority 6 */
789 	u8	res83[12];
790 	u32	iidr6;		/* Internal IRQ Destination 6 */
791 	u8	res84[12];
792 	u32	iivpr7;		/* Internal IRQ Vector/Priority 7 */
793 	u8	res85[12];
794 	u32	iidr7;		/* Internal IRQ Destination 7 */
795 	u8	res86[12];
796 	u32	iivpr8;		/* Internal IRQ Vector/Priority 8 */
797 	u8	res87[12];
798 	u32	iidr8;		/* Internal IRQ Destination 8 */
799 	u8	res88[12];
800 	u32	iivpr9;		/* Internal IRQ Vector/Priority 9 */
801 	u8	res89[12];
802 	u32	iidr9;		/* Internal IRQ Destination 9 */
803 	u8	res90[12];
804 	u32	iivpr10;	/* Internal IRQ Vector/Priority 10 */
805 	u8	res91[12];
806 	u32	iidr10;		/* Internal IRQ Destination 10 */
807 	u8	res92[12];
808 	u32	iivpr11;	/* Internal IRQ Vector/Priority 11 */
809 	u8	res93[12];
810 	u32	iidr11;		/* Internal IRQ Destination 11 */
811 	u8	res94[12];
812 	u32	iivpr12;	/* Internal IRQ Vector/Priority 12 */
813 	u8	res95[12];
814 	u32	iidr12;		/* Internal IRQ Destination 12 */
815 	u8	res96[12];
816 	u32	iivpr13;	/* Internal IRQ Vector/Priority 13 */
817 	u8	res97[12];
818 	u32	iidr13;		/* Internal IRQ Destination 13 */
819 	u8	res98[12];
820 	u32	iivpr14;	/* Internal IRQ Vector/Priority 14 */
821 	u8	res99[12];
822 	u32	iidr14;		/* Internal IRQ Destination 14 */
823 	u8	res100[12];
824 	u32	iivpr15;	/* Internal IRQ Vector/Priority 15 */
825 	u8	res101[12];
826 	u32	iidr15;		/* Internal IRQ Destination 15 */
827 	u8	res102[12];
828 	u32	iivpr16;	/* Internal IRQ Vector/Priority 16 */
829 	u8	res103[12];
830 	u32	iidr16;		/* Internal IRQ Destination 16 */
831 	u8	res104[12];
832 	u32	iivpr17;	/* Internal IRQ Vector/Priority 17 */
833 	u8	res105[12];
834 	u32	iidr17;		/* Internal IRQ Destination 17 */
835 	u8	res106[12];
836 	u32	iivpr18;	/* Internal IRQ Vector/Priority 18 */
837 	u8	res107[12];
838 	u32	iidr18;		/* Internal IRQ Destination 18 */
839 	u8	res108[12];
840 	u32	iivpr19;	/* Internal IRQ Vector/Priority 19 */
841 	u8	res109[12];
842 	u32	iidr19;		/* Internal IRQ Destination 19 */
843 	u8	res110[12];
844 	u32	iivpr20;	/* Internal IRQ Vector/Priority 20 */
845 	u8	res111[12];
846 	u32	iidr20;		/* Internal IRQ Destination 20 */
847 	u8	res112[12];
848 	u32	iivpr21;	/* Internal IRQ Vector/Priority 21 */
849 	u8	res113[12];
850 	u32	iidr21;		/* Internal IRQ Destination 21 */
851 	u8	res114[12];
852 	u32	iivpr22;	/* Internal IRQ Vector/Priority 22 */
853 	u8	res115[12];
854 	u32	iidr22;		/* Internal IRQ Destination 22 */
855 	u8	res116[12];
856 	u32	iivpr23;	/* Internal IRQ Vector/Priority 23 */
857 	u8	res117[12];
858 	u32	iidr23;		/* Internal IRQ Destination 23 */
859 	u8	res118[12];
860 	u32	iivpr24;	/* Internal IRQ Vector/Priority 24 */
861 	u8	res119[12];
862 	u32	iidr24;		/* Internal IRQ Destination 24 */
863 	u8	res120[12];
864 	u32	iivpr25;	/* Internal IRQ Vector/Priority 25 */
865 	u8	res121[12];
866 	u32	iidr25;		/* Internal IRQ Destination 25 */
867 	u8	res122[12];
868 	u32	iivpr26;	/* Internal IRQ Vector/Priority 26 */
869 	u8	res123[12];
870 	u32	iidr26;		/* Internal IRQ Destination 26 */
871 	u8	res124[12];
872 	u32	iivpr27;	/* Internal IRQ Vector/Priority 27 */
873 	u8	res125[12];
874 	u32	iidr27;		/* Internal IRQ Destination 27 */
875 	u8	res126[12];
876 	u32	iivpr28;	/* Internal IRQ Vector/Priority 28 */
877 	u8	res127[12];
878 	u32	iidr28;		/* Internal IRQ Destination 28 */
879 	u8	res128[12];
880 	u32	iivpr29;	/* Internal IRQ Vector/Priority 29 */
881 	u8	res129[12];
882 	u32	iidr29;		/* Internal IRQ Destination 29 */
883 	u8	res130[12];
884 	u32	iivpr30;	/* Internal IRQ Vector/Priority 30 */
885 	u8	res131[12];
886 	u32	iidr30;		/* Internal IRQ Destination 30 */
887 	u8	res132[12];
888 	u32	iivpr31;	/* Internal IRQ Vector/Priority 31 */
889 	u8	res133[12];
890 	u32	iidr31;		/* Internal IRQ Destination 31 */
891 	u8	res134[4108];
892 	u32	mivpr0;		/* Messaging IRQ Vector/Priority 0 */
893 	u8	res135[12];
894 	u32	midr0;		/* Messaging IRQ Destination 0 */
895 	u8	res136[12];
896 	u32	mivpr1;		/* Messaging IRQ Vector/Priority 1 */
897 	u8	res137[12];
898 	u32	midr1;		/* Messaging IRQ Destination 1 */
899 	u8	res138[12];
900 	u32	mivpr2;		/* Messaging IRQ Vector/Priority 2 */
924 } ccsr_pic_t;  argument