Lines Matching defs:ccsr_gur
1587 typedef struct ccsr_gur { struct
1588 u32 porsr1; /* POR status 1 */
1589 u32 porsr2; /* POR status 2 */
1596 u8 res_008[0x20-0x8];
1597 u32 gpporcr1; /* General-purpose POR configuration */
1598 u32 gpporcr2; /* General-purpose POR configuration 2 */
1599 u32 dcfg_fusesr; /* Fuse status register */
1604 u8 res_02c[0x70-0x2c];
1605 u32 devdisr; /* Device disable control */
1606 u32 devdisr2; /* Device disable control 2 */
1607 u32 devdisr3; /* Device disable control 3 */
1608 u32 devdisr4; /* Device disable control 4 */
1610 u32 devdisr5; /* Device disable control 5 */
1727 u32 powmgtcsr; /* Power management status & control */
1729 u8 res8[12];
1730 u32 coredisru; /* uppper portion for support of 64 cores */
1731 u32 coredisrl; /* lower portion for support of 64 cores */
1732 u8 res9[8];
1733 u32 pvr; /* Processor version */
1734 u32 svr; /* System version */
1735 u8 res10[8];
1736 u32 rstcr; /* Reset control */
1737 u32 rstrqpblsr; /* Reset request preboot loader status */
1738 u8 res11[8];
1739 u32 rstrqmr1; /* Reset request mask */
1743 u8 res12[4];
1744 u32 rstrqsr1; /* Reset request status */
1745 u8 res13[4];
1746 u8 res14[4];
1747 u32 rstrqwdtmrl; /* Reset request WDT mask */
1748 u8 res15[4];
1749 u32 rstrqwdtsrl; /* Reset request WDT status */
1750 u8 res16[4];
1751 u32 brrl; /* Boot release */
1752 u8 res17[24];
1753 u32 rcwsr[16]; /* Reset control word status */
1893 u8 res18[192];
1894 u32 scratchrw[4]; /* Scratch Read/Write */
1895 u8 res19[240];
1896 u32 scratchw1r[4]; /* Scratch Read (Write once) */
1897 u8 res20[240];
1898 u32 scrtsr[8]; /* Core reset status */
1899 u8 res21[224];
1900 u32 pex1liodnr; /* PCI Express 1 LIODN */
1901 u32 pex2liodnr; /* PCI Express 2 LIODN */
1902 u32 pex3liodnr; /* PCI Express 3 LIODN */
1903 u32 pex4liodnr; /* PCI Express 4 LIODN */
1904 u32 rio1liodnr; /* RIO 1 LIODN */
1905 u32 rio2liodnr; /* RIO 2 LIODN */
1906 u32 rio3liodnr; /* RIO 3 LIODN */
1907 u32 rio4liodnr; /* RIO 4 LIODN */
1908 u32 usb1liodnr; /* USB 1 LIODN */
1909 u32 usb2liodnr; /* USB 2 LIODN */
1910 u32 usb3liodnr; /* USB 3 LIODN */
1911 u32 usb4liodnr; /* USB 4 LIODN */
1912 u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */
1913 u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */
1914 u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */
1915 u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */
1916 u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */
1917 u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */
1918 u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */
1919 u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */
1920 u32 sata1liodnr; /* SATA 1 LIODN */
1921 u32 sata2liodnr; /* SATA 2 LIODN */
1922 u32 sata3liodnr; /* SATA 3 LIODN */
1923 u32 sata4liodnr; /* SATA 4 LIODN */
1924 u8 res22[20];
1925 u32 tdmliodnr; /* TDM LIODN */
1926 u32 qeliodnr; /* QE LIODN */
1927 u8 res_57c[4];
1928 u32 dma1liodnr; /* DMA 1 LIODN */
1929 u32 dma2liodnr; /* DMA 2 LIODN */
1930 u32 dma3liodnr; /* DMA 3 LIODN */
1931 u32 dma4liodnr; /* DMA 4 LIODN */
1932 u8 res23[48];
1933 u8 res24[64];
1934 u32 pblsr; /* Preboot loader status */
1935 u32 pamubypenr; /* PAMU bypass enable */
1936 u32 dmacr1; /* DMA control */
1937 u8 res25[4];
1938 u32 gensr1; /* General status */
1939 u8 res26[12];
1940 u32 gencr1; /* General control */
1941 u8 res27[12];
1942 u8 res28[4];
1943 u32 cgensrl; /* Core general status */
1967 } ccsr_gur_t; argument
2117 typedef struct ccsr_gur { struct
2118 u32 porpllsr; /* POR PLL ratio status */
2139 u32 porbmsr; /* POR boot mode status */
2147 u32 porimpscr; /* POR I/O impedance status & control */
2148 u32 pordevsr; /* POR I/O device status regsiter */
2190 u32 pordbgmsr; /* POR debug mode status */
2191 u32 pordevsr2; /* POR I/O device status 2 */
2199 u8 res1[8];
2200 u32 gpporcr; /* General-purpose POR configuration */
2201 u8 res2[12];
2203 u32 gencfgr; /* General Configuration Register */
2206 u32 gpiocr; /* GPIO control */
2208 u8 res3[12];
2210 u32 plppar1; /* Platform port pin assignment 1 */
2211 u32 plppar2; /* Platform port pin assignment 2 */
2212 u32 plpdir1; /* Platform port pin direction 1 */
2213 u32 plpdir2; /* Platform port pin direction 2 */
2215 u32 gpoutdr; /* General-purpose output data */
2216 u8 res4[12];
2218 u32 gpindr; /* General-purpose input data */
2219 u8 res5[12];
2220 u32 pmuxcr; /* Alt. function signal multiplex control */
2348 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
2423 u32 pmuxcr3;
2446 u32 pmuxcr4;
2448 u8 res6[8];
2450 u32 devdisr; /* Device disable control */
2474 u8 res7[12];
2475 u32 powmgtcsr; /* Power management status & control */
2476 u8 res8[12];
2477 u32 mcpsumr; /* Machine check summary */
2478 u8 res9[12];
2479 u32 pvr; /* Processor version */
2480 u32 svr; /* System version */
2481 u8 res10[8];
2482 u32 rstcr; /* Reset control */
2484 u8 res11a[76];
2485 par_io_t qe_par_io[7];
2486 u8 res11b[1600];
2488 u8 res11a[12];
2489 u32 iovselsr;
2490 u8 res11b[60];
2491 par_io_t qe_par_io[3];
2492 u8 res11c[1496];
2494 u8 res11a[1868];
2519 } ccsr_gur_t; argument