include/asm/immap_85xx.h

3115 struct ccsr_cluster_l2 {  struct
3116 	u32 l2csr0;	/* 0x000 L2 cache control and status register 0 */
3117 	u32 l2csr1;	/* 0x004 L2 cache control and status register 1 */
3118 	u32 l2cfg0;	/* 0x008 L2 cache configuration register 0 */
3119 	u8  res_0c[500];/* 0x00c - 0x1ff */
3120 	u32 l2pir0;	/* 0x200 L2 cache partitioning ID register 0 */
3121 	u8  res_204[4];
3122 	u32 l2par0;	/* 0x208 L2 cache partitioning allocation register 0 */
3123 	u32 l2pwr0;	/* 0x20c L2 cache partitioning way register 0 */
3124 	u32 l2pir1;	/* 0x210 L2 cache partitioning ID register 1 */
3125 	u8  res_214[4];
3126 	u32 l2par1;	/* 0x218 L2 cache partitioning allocation register 1 */
3127 	u32 l2pwr1;	/* 0x21c L2 cache partitioning way register 1 */
3128 	u32 u2pir2;	/* 0x220 L2 cache partitioning ID register 2 */
3129 	u8  res_224[4];
3130 	u32 l2par2;	/* 0x228 L2 cache partitioning allocation register 2 */
3131 	u32 l2pwr2;	/* 0x22c L2 cache partitioning way register 2 */
3132 	u32 l2pir3;	/* 0x230 L2 cache partitioning ID register 3 */
3133 	u8  res_234[4];
3134 	u32 l2par3;	/* 0x238 L2 cache partitining allocation register 3 */
3135 	u32 l2pwr3;	/* 0x23c L2 cache partitining way register 3 */
3136 	u32 l2pir4;	/* 0x240 L2 cache partitioning ID register 3 */
3137 	u8  res244[4];
3138 	u32 l2par4;	/* 0x248 L2 cache partitioning allocation register 3 */
3139 	u32 l2pwr4;	/* 0x24c L2 cache partitioning way register 3 */
3140 	u32 l2pir5;	/* 0x250 L2 cache partitioning ID register 3 */
3141 	u8  res_254[4];
3142 	u32 l2par5;	/* 0x258 L2 cache partitioning allocation register 3 */
3143 	u32 l2pwr5;	/* 0x25c L2 cache partitioning way register 3 */
3144 	u32 l2pir6;	/* 0x260 L2 cache partitioning ID register 3 */
3145 	u8  res_264[4];
3146 	u32 l2par6;	/* 0x268 L2 cache partitioning allocation register 3 */
3147 	u32 l2pwr6;	/* 0x26c L2 cache partitioning way register 3 */
3148 	u32 l2pir7;	/* 0x270 L2 cache partitioning ID register 3 */
3149 	u8  res274[4];
3150 	u32 l2par7;	/* 0x278 L2 cache partitioning allocation register 3 */
3151 	u32 l2pwr7;	/* 0x27c L2 cache partitioning way register 3 */
3152 	u8  res_280[0xb80]; /* 0x280 - 0xdff */
3153 	u32 l2errinjhi;	/* 0xe00 L2 cache error injection mask high */
3154 	u32 l2errinjlo;	/* 0xe04 L2 cache error injection mask low */
3155 	u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
3156 	u8  res_e0c[20];	/* 0xe0c - 0x01f */
3157 	u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
3158 	u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
3159 	u32 l2captecc;	/* 0xe28 L2 cache error capture ECC syndrome */
3160 	u8  res_e2c[20];	/* 0xe2c - 0xe3f */
3161 	u32 l2errdet;	/* 0xe40 L2 cache error detect */
3162 	u32 l2errdis;	/* 0xe44 L2 cache error disable */
3163 	u32 l2errinten;	/* 0xe48 L2 cache error interrupt enable */
3164 	u32 l2errattr;	/* 0xe4c L2 cache error attribute */
3165 	u32 l2erreaddr;	/* 0xe50 L2 cache error extended address */
3166 	u32 l2erraddr;	/* 0xe54 L2 cache error address */
3167 	u32 l2errctl;	/* 0xe58 L2 cache error control */