include/asm/fsl_pci.h

69 typedef struct ccsr_pci {  struct
70 	u32	cfg_addr;	/* 0x000 - PCI Configuration Address Register */
71 	u32	cfg_data;	/* 0x004 - PCI Configuration Data Register */
72 	u32	int_ack;	/* 0x008 - PCI Interrupt Acknowledge Register */
73 	u32	out_comp_to;	/* 0x00C - PCI Outbound Completion Timeout Register */
74 	u32	out_conf_to;	/* 0x010 - PCI Configuration Timeout Register */
75 	u32	config;		/* 0x014 - PCIE CONFIG Register */
76 	u32	int_status;	/* 0x018 - PCIE interrupt status register */
77 	char	res2[4];
78 	u32	pme_msg_det;	/* 0x020 - PCIE PME & message detect register */
79 	u32	pme_msg_dis;	/* 0x024 - PCIE PME & message disable register */
80 	u32	pme_msg_int_en;	/* 0x028 - PCIE PME & message interrupt enable register */
81 	u32	pm_command;	/* 0x02c - PCIE PM Command register */
82 	char	res3[2188];	/*     (0x8bc - 0x30 = 2188) */
83 	u32	dbi_ro_wr_en;	/* 0x8bc - DBI read only write enable reg */
84 	char	res4[824];	/*     (0xbf8 - 0x8c0 = 824) */
85 	u32	block_rev1;	/* 0xbf8 - PCIE Block Revision register 1 */
86 	u32	block_rev2;	/* 0xbfc - PCIE Block Revision register 2 */
88 	pot_t	pot[5];		/* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
89 	u32	res5[24];
90 	pit_t	pmit;		/* 0xd00 - 0xd9c Inbound ATMU's MSI */
91 	u32	res6[24];
92 	pit_t	pit[4];		/* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */
147 	u32	pedr;		/* 0xe00 - PCI Error Detect Register */
148 	u32	pecdr;		/* 0xe04 - PCI Error Capture Disable Register */
149 	u32	peer;		/* 0xe08 - PCI Error Interrupt Enable Register */
150 	u32	peattrcr;	/* 0xe0c - PCI Error Attributes Capture Register */
151 	u32	peaddrcr;	/* 0xe10 - PCI Error Address Capture Register */
153 	u32	peextaddrcr;	/* 0xe14 - PCI	Error Extended Address Capture Register */
154 	u32	pedlcr;		/* 0xe18 - PCI Error Data Low Capture Register */
155 	u32	pedhcr;		/* 0xe1c - PCI Error Error Data High Capture Register */
156 	u32	gas_timr;	/* 0xe20 - PCI Gasket Timer Register */
158 	char	res22[4];
159 	u32	perr_cap0;	/* 0xe28 - PCIE Error Capture Register 0 */
160 	u32	perr_cap1;	/* 0xe2c - PCIE Error Capture Register 1 */
161 	u32	perr_cap2;	/* 0xe30 - PCIE Error Capture Register 2 */
162 	u32	perr_cap3;	/* 0xe34 - PCIE Error Capture Register 3 */
163 	char	res23[200];
164 	u32	pdb_stat;	/* 0xf00 - PCIE Debug Status */
165 	char	res24[16];
166 	u32	pex_csr0;	/* 0xf14 - PEX Control/Status register 0*/
167 	u32	pex_csr1;	/* 0xf18 - PEX Control/Status register 1*/
168 	char	res25[228];