Lines Matching refs:r3
88 mr r24, r3
91 mfspr r3,SPRN_SVR
92 rlwinm r3,r3,0,0xff
94 cmpw r3,r4
99 cmpw r3,r4
111 mfspr r3,SPRN_HDBCR0
113 rlwimi r3,r4,0,0x1f8
114 mtspr SPRN_HDBCR0,r3
121 mfspr r3, SPRN_HDBCR0
122 oris r3, r3, 0x0080
123 mtspr SPRN_HDBCR0, r3
135 mfspr r3, SPRN_L2CSR0
138 and. r4, r3, r2
141 mfspr r3, SPRN_L2CSR0
145 or r3, r2, r3
148 mtspr SPRN_L2CSR0,r3
151 mfspr r3, SPRN_L2CSR0
152 and. r1, r3, r2
155 mfspr r3, SPRN_L2CSR0
158 andc r4, r3, r2
316 mfspr r3,PVR
317 andi. r3,r3, 0xff
318 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
327 mfspr r3,SPRN_HDBCR1
328 oris r3,r3,0x0100
329 mtspr SPRN_HDBCR1,r3
403 mfspr r3, MAS1
405 andc r3, r3, r2 /* Clear the TSIZE bits */
406 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
407 oris r3, r3, MAS1_IPROT@h
408 mtspr MAS1, r3
414 lis r3, MAS2_EPN@h
415 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
417 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
420 andc r2, r2, r3
433 andc r2, r2, r3
452 li r3, 0
453 mtspr MAS1, r3
454 1: cmpw r3, r14
455 rlwinm r5, r3, 16, MAS0_ESEL_MSK
456 addi r3, r3, 1
467 2: cmpw r3, r4
536 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
546 0, r3 /* The default CCSR address is always a 32-bit number */
696 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
697 delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
711 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
715 lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
716 ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
718 stw r4, 4(r3)
722 stw r4, 0(r3) /* invalidate L2 */
725 lwz r0, 0(r3)
735 stw r4, 0(r3) /* enable L2 parity/ECC error checking */
738 lwz r0, 0(r3)
747 stw r4, 0(r3) /* enable L2 */
750 lwz r0, 0(r3)
757 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
776 mfspr r3,SPRN_L1CSR1
777 and. r1,r3,r2
780 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
781 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
782 mtspr SPRN_L1CSR1,r3
785 mfspr r3,SPRN_L1CSR1
786 andi. r1,r3,L1CSR1_ICE@l
794 mfspr r3,SPRN_L1CSR0
795 and. r1,r3,r2
798 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
799 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
800 mtspr SPRN_L1CSR0,r3
803 mfspr r3,SPRN_L1CSR0
804 andi. r1,r3,L1CSR0_DCE@l
831 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
832 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
838 mtspr MAS3, r3
847 lis r3, DCSRBAR_LAWAR@h
848 ori r3, r3, DCSRBAR_LAWAR@l
853 stw r3, 0xc08(r7) /* LAWAR0 */
856 lwz r3, 0xc08(r7) /* LAWAR0 */
868 li r3, MAS3_SW|MAS3_SR
873 mtspr MAS3, r3
882 li r3, 1
884 stw r3, CTBENR@l(r4)
885 lwz r3, CTBENR@l(r4)
886 twi 0,r3,0
890 addis r3, r7, \offset@ha
892 addi r3, r3, \offset@l
898 addis r3, r6, \offset@ha
900 addi r3, r3, \offset@l
920 2: mflr r3
921 tlbsx 0, r3
932 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
933 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
936 mtspr SPRN_L1CSR1,r3
940 and. r4,r4,r3
943 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
944 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
947 mtspr SPRN_L1CSR1,r3
951 and. r4,r4,r3
957 li r3, 0
959 mtspr MAS1, r3
965 li r3, 0
966 stw r3, 0xc08(r7) /* LAWAR0 */
967 lwz r3, 0xc08(r7)
972 li r3, 0
974 mtspr MAS1, r3
1024 stw r4, 0(r3)
1138 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1139 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1147 dcbz r0,r3
1149 dcbtls 2, r0, r3
1150 dcbtls 0, r0, r3
1152 dcbtls 0, r0, r3
1154 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1164 lis r3,CONFIG_SYS_MONITOR_BASE@h
1165 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
1166 addi r3,r3,_start_cont - _start
1167 mtlr r3
1183 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
1184 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
1192 subi r3,r3,((CONFIG_VAL(SYS_MALLOC_F_LEN)+16+15)&~0xf)
1203 cmplw r4,r3
1210 addi r3,r3,16 /* Pre-relocation malloc area */
1211 stw r3,GD_MALLOC_BASE(r4)
1212 subi r3,r3,16
1215 stw r0,0(r3) /* Terminate Back Chain */
1216 stw r0,+4(r3) /* NULL return address. */
1217 mr r1,r3 /* Transfer to SP(r1) */
1222 mr r3, r24
1227 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
1228 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
1229 mtmsr r3
1264 addi r3,r1,STACK_FRAME_OVERHEAD
1271 addi r3,r1,STACK_FRAME_OVERHEAD
1385 lis r3,0
1386 ori r3,r3,L1CSR1_ICE
1387 andc r0,r0,r3
1394 mfspr r3,L1CSR1
1395 andi. r3,r3,L1CSR1_ICE
1415 mfspr r3,L1CSR0
1418 andc r3,r3,r4
1419 mtspr L1CSR0,r3
1425 mfspr r3,L1CSR0
1426 andi. r3,r3,L1CSR0_DCE
1435 lbz r3,0x0000(r3)
1444 stb r4,0x0000(r3)
1454 sth r4,0x0000(r3)
1464 sthbrx r4,r0,r3
1474 stw r4,0x0000(r3)
1484 stwbrx r4,r0,r3
1494 lhz r3,0x0000(r3)
1503 lhbrx r3,r0,r3
1521 lwbrx r3,r0,r3
1532 mtspr MAS0,r3
1539 li r3,0
1541 mtspr MAS8,r3
1562 mr r1,r3 /* Set new stack pointer */
1568 mr r3,r5 /* Destination Address */
1593 cmplw cr1,r3,r4
1602 la r7,-4(r3)
1610 add r7,r3,r0
1620 add r5,r3,r5
1623 andc r3,r3,r0
1624 mr r4,r3
1630 mr r4,r3
1669 la r3,GOT(_GOT2_TABLE_)
1672 sub r11,r3,r11
1673 addi r3,r3,-4
1674 1: lwzu r0,4(r3)
1678 stw r0,0(r3)
1686 lwz r3,GOT(_FIXUP_TABLE_)
1689 addi r3,r3,-4
1691 3: lwzu r4,4(r3)
1695 stw r4,0(r3)
1704 lwz r3,GOT(__bss_start)
1707 cmplw 0,r3,r4
1712 stw r0,0(r3)
1713 addi r3,r3,4
1714 cmplw 0,r3,r4
1718 mr r3,r9 /* Init Data pointer */
1736 mtspr IVPR,r3
1776 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1777 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1782 1: dcbi r0,r3
1784 dcblc 2, r0, r3
1785 dcblc 0, r0, r3
1787 dcblc r0,r3
1789 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1794 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1795 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1796 tlbivax 0,r3
1797 addi r3,r3,0x1000
1798 tlbivax 0,r3
1799 addi r3,r3,0x1000
1800 tlbivax 0,r3
1801 addi r3,r3,0x1000
1802 tlbivax 0,r3
1808 mfspr r3,SPRN_L1CFG0
1810 rlwinm r5,r3,9,3 /* Extract cache block size */
1820 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1835 1: lwz r3,0(r4) /* Load... */