Lines Matching refs:li
80 li r1,MSR_DE
93 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
98 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
104 li r27,0
107 1: li r27,1 /* Remember for later that we have the erratum */
112 li r4,0x48
170 li r0,2
226 li \scratch, 0
238 li \scratch, 0
255 li r4,CriticalInput@l
257 li r4,MachineCheck@l
259 li r4,DataStorage@l
261 li r4,InstStorage@l
263 li r4,ExtInterrupt@l
265 li r4,Alignment@l
267 li r4,ProgramCheck@l
269 li r4,FPUnavailable@l
271 li r4,SystemCall@l
274 li r4,Decrementer@l
276 li r4,IntervalTimer@l
278 li r4,WatchdogTimer@l
280 li r4,DataTLBError@l
282 li r4,InstructionTLBError@l
284 li r4,DebugBreakpoint@l
289 li r0,0x0000
315 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
393 li r2, 0
404 li r2, 0xF80
445 li r0, TLBIVAX_ALL | TLBIVAX_TLB0
452 li r3, 0
648 li r1, 0
717 li r4, 33 /* stash id */
767 li r2,(32 + 0)
846 li r0, 0
866 li r6, 0 /* DCSR effective address */
868 li r3, MAS3_SW|MAS3_SR
869 li r4, 0
882 li r3, 1
957 li r3, 0
965 li r3, 0
972 li r3, 0
1145 li r0,0
1199 li r0,0
1214 li r0,0
1307 li r22,0
1317 li r4,0
1539 li r3,0
1573 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1668 li r0,__got2_entries@sectoff@l
1685 li r0,__fixup_entries@sectoff@l
1710 li r0,0
1814 li r4,32