32 	struct pci_controller *hose = &pci_hose[bus];  in pci_init_bus()  local
45 		hose->regions[i] = *reg;  in pci_init_bus()
46 		hose->region_count++;  in pci_init_bus()
72 	i = hose->region_count++;  in pci_init_bus()
73 	hose->regions[i].bus_start = 0;  in pci_init_bus()
74 	hose->regions[i].phys_start = 0;  in pci_init_bus()
75 	hose->regions[i].size = gd->ram_size;  in pci_init_bus()
76 	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;  in pci_init_bus()
78 	hose->first_busno = pci_last_busno() + 1;  in pci_init_bus()
79 	hose->last_busno = 0xff;  in pci_init_bus()
81 	pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,  in pci_init_bus()
84 	pci_register_hose(hose);  in pci_init_bus()
90 	dev = PCI_BDF(hose->first_busno, 0, 0);  in pci_init_bus()
91 	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);  in pci_init_bus()
93 	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);  in pci_init_bus()
98 	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);  in pci_init_bus()
99 	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);  in pci_init_bus()
100 	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);  in pci_init_bus()
109 	hose->last_busno = pci_hose_scan(hose);  in pci_init_bus()
170 	struct pci_controller *hose = &pci_hose[bus];  in mpc83xx_pcislave_unlock()  local
175 	dev = PCI_BDF(hose->first_busno, 0, 0);  in mpc83xx_pcislave_unlock()
176 	pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, &reg16);  in mpc83xx_pcislave_unlock()
178 	pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);  in mpc83xx_pcislave_unlock()
181 	hose->last_busno = pci_hose_scan(hose);  in mpc83xx_pcislave_unlock()