Lines Matching refs:regs
224 void __iomem *regs; in ddr_init() local
227 regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, in ddr_init()
231 writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF); in ddr_init()
235 writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE); in ddr_init()
239 writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST); in ddr_init()
241 writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2); in ddr_init()
245 writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX); in ddr_init()
249 writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG); in ddr_init()
251 writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2); in ddr_init()
253 writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3); in ddr_init()
257 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
261 writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR); in ddr_init()
265 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
269 writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE); in ddr_init()
273 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
277 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
281 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
283 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
287 writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE); in ddr_init()
291 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
295 writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH); in ddr_init()
299 writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_init()
302 writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
304 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
306 writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
309 regs + QCA953X_DDR_REG_CTL_CONF); in ddr_init()
313 writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE); in ddr_init()
317 writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST); in ddr_init()
319 writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2); in ddr_init()
323 writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX); in ddr_init()
327 writel(DDR2_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG); in ddr_init()
329 writel(DDR2_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2); in ddr_init()
331 writel(DDR2_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3); in ddr_init()
335 writel(DDR2_CONF_VAL, regs + QCA953X_DDR_REG_DDR2_CONFIG); in ddr_init()
339 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
343 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
347 writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
351 writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR); in ddr_init()
355 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
359 writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE); in ddr_init()
363 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
367 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
371 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
373 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
377 writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE); in ddr_init()
381 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
385 writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR); in ddr_init()
389 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
393 writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR); in ddr_init()
397 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
401 writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH); in ddr_init()
405 writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_init()
408 writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
414 void __iomem *regs; in ddr_tap_tuning() local
417 regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, in ddr_tap_tuning()
420 tap_val = readl(regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_tap_tuning()
427 writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_tap_tuning()
428 writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
430 writel(DDR_BIST_COMP_CNT(8), regs + DDR_REG_BIST_COMP_ADDR_1); in ddr_tap_tuning()
431 writel(DDR_BIST_MASK_ADDR_VAL, regs + DDR_REG_BIST_MASK_ADDR_0); in ddr_tap_tuning()
432 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_1); in ddr_tap_tuning()
433 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_0); in ddr_tap_tuning()
434 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_1); in ddr_tap_tuning()
435 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_0); in ddr_tap_tuning()
436 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_1); in ddr_tap_tuning()
437 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_0); in ddr_tap_tuning()
438 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_1); in ddr_tap_tuning()
439 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_0); in ddr_tap_tuning()
442 writel(DDR_BIST_TEST_START, regs + DDR_REG_BIST); in ddr_tap_tuning()
445 val = readl(regs + DDR_REG_BIST_STATUS); in ddr_tap_tuning()
449 writel(0, regs + DDR_REG_BIST); in ddr_tap_tuning()
470 writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_tap_tuning()
471 writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()