Lines Matching refs:AR71XX_DDR_REG_CONTROL
126 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
132 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
137 writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
143 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
149 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
152 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
155 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
156 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
161 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
167 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
172 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
195 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
201 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
207 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
210 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
216 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()