include/asm/mipsregs.h

9  * SPDX-License-Identifier:	GPL-2.0
81  * by Linux.  A future ELKS port might take make Linux run on them
128 /* MIPS32/64 EntryLo bit definitions */
130 #define MIPS_ENTRYLO_XI		(_ULCAST_(1) << (BITS_PER_LONG - 2))
131 #define MIPS_ENTRYLO_RI		(_ULCAST_(1) << (BITS_PER_LONG - 1))
190 /* MIPS32/64 EntryHI bit definitions */
454 /* Bits specific to the MIPS32/64 PRA.	*/
464  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
543 /* bits 10:8 in FTLB-only configurations */
545 /* bits 12:8 in VTLB-FTLB only configurations */
588 #define MIPS_MAAR_ADDR		((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
595 #define MIPS_CMGCRF_BASE	(~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
598  * Bits in the MIPS32 Memory Segmentation registers.
712  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
726  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
748  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
820 #define FPU_CSR_RD	0x3	/* towards -Infinity */
840  * microMIPS instructions can be 16-bit or 32-bit in length. This
841  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
865  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
867  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1012  * physical address space running the 32-bit kernel.  That's none atm :-)
1286  * MIPS32 / MIPS64 performance counters