Lines Matching defs:int0_ctrl
19 typedef struct int0_ctrl { struct
21 u32 iprh0; /* 0x00 Pending High */
22 u32 iprl0; /* 0x04 Pending Low */
23 u32 imrh0; /* 0x08 Mask High */
24 u32 imrl0; /* 0x0C Mask Low */
25 u32 frch0; /* 0x10 Force High */
26 u32 frcl0; /* 0x14 Force Low */
28 u8 irlr; /* 0x18 */
29 u8 iacklpr; /* 0x19 */
30 u16 res1[19]; /* 0x1a - 0x3c */
32 u16 res1; /* 0x18 - 0x19 */
33 u16 icfg0; /* 0x1A Configuration */
34 u8 simr0; /* 0x1C Set Interrupt Mask */
35 u8 cimr0; /* 0x1D Clear Interrupt Mask */
36 u8 clmask0; /* 0x1E Current Level Mask */
37 u8 slmask; /* 0x1F Saved Level Mask */
38 u32 res2[8]; /* 0x20 - 0x3F */
40 u8 icr0[64]; /* 0x40 - 0x7F Control registers */
41 u32 res3[24]; /* 0x80 - 0xDF */
42 u8 swiack0; /* 0xE0 Software Interrupt ack */
43 u8 res4[3]; /* 0xE1 - 0xE3 */
44 u8 L1iack0; /* 0xE4 Level n interrupt ack */
45 u8 res5[3]; /* 0xE5 - 0xE7 */
46 u8 L2iack0; /* 0xE8 Level n interrupt ack */
47 u8 res6[3]; /* 0xE9 - 0xEB */
48 u8 L3iack0; /* 0xEC Level n interrupt ack */
49 u8 res7[3]; /* 0xED - 0xEF */
50 u8 L4iack0; /* 0xF0 Level n interrupt ack */
51 u8 res8[3]; /* 0xF1 - 0xF3 */
52 u8 L5iack0; /* 0xF4 Level n interrupt ack */
53 u8 res9[3]; /* 0xF5 - 0xF7 */
54 u8 L6iack0; /* 0xF8 Level n interrupt ack */
55 u8 resa[3]; /* 0xF9 - 0xFB */
56 u8 L7iack0; /* 0xFC Level n interrupt ack */
57 u8 resb[3]; /* 0xFD - 0xFF */