Lines Matching defs:edma_ctrl
18 typedef struct edma_ctrl { struct
19 u32 cr; /* 0x00 Control Register */
20 u32 es; /* 0x04 Error Status Register */
21 u16 res1[3]; /* 0x08 - 0x0D */
22 u16 erq; /* 0x0E Enable Request Register */
23 u16 res2[3]; /* 0x10 - 0x15 */
24 u16 eei; /* 0x16 Enable Error Interrupt Request */
25 u8 serq; /* 0x18 Set Enable Request */
26 u8 cerq; /* 0x19 Clear Enable Request */
27 u8 seei; /* 0x1A Set En Error Interrupt Request */
28 u8 ceei; /* 0x1B Clear En Error Interrupt Request */
29 u8 cint; /* 0x1C Clear Interrupt Enable */
30 u8 cerr; /* 0x1D Clear Error */
31 u8 ssrt; /* 0x1E Set START Bit */
32 u8 cdne; /* 0x1F Clear DONE Status Bit */
33 u16 res3[3]; /* 0x20 - 0x25 */
34 u16 intr; /* 0x26 Interrupt Request */
35 u16 res4[3]; /* 0x28 - 0x2D */
36 u16 err; /* 0x2E Error Register */
37 u32 res5[52]; /* 0x30 - 0xFF */
38 u8 dchpri0; /* 0x100 Channel 0 Priority */
39 u8 dchpri1; /* 0x101 Channel 1 Priority */
40 u8 dchpri2; /* 0x102 Channel 2 Priority */
41 u8 dchpri3; /* 0x103 Channel 3 Priority */
42 u8 dchpri4; /* 0x104 Channel 4 Priority */
43 u8 dchpri5; /* 0x105 Channel 5 Priority */
44 u8 dchpri6; /* 0x106 Channel 6 Priority */
45 u8 dchpri7; /* 0x107 Channel 7 Priority */
46 u8 dchpri8; /* 0x108 Channel 8 Priority */
47 u8 dchpri9; /* 0x109 Channel 9 Priority */
48 u8 dchpri10; /* 0x110 Channel 10 Priority */
49 u8 dchpri11; /* 0x111 Channel 11 Priority */
50 u8 dchpri12; /* 0x112 Channel 12 Priority */
51 u8 dchpri13; /* 0x113 Channel 13 Priority */
52 u8 dchpri14; /* 0x114 Channel 14 Priority */
53 u8 dchpri15; /* 0x115 Channel 15 Priority */