Lines Matching refs:reset_set_enable
180 reset_set_enable(PERIPH_ID_CACHE2, 0); in tegra124_init_clocks()
181 reset_set_enable(PERIPH_ID_GPIO, 0); in tegra124_init_clocks()
182 reset_set_enable(PERIPH_ID_TMR, 0); in tegra124_init_clocks()
183 reset_set_enable(PERIPH_ID_COP, 0); in tegra124_init_clocks()
184 reset_set_enable(PERIPH_ID_EMC, 0); in tegra124_init_clocks()
185 reset_set_enable(PERIPH_ID_I2C5, 0); in tegra124_init_clocks()
186 reset_set_enable(PERIPH_ID_APBDMA, 0); in tegra124_init_clocks()
187 reset_set_enable(PERIPH_ID_MEM, 0); in tegra124_init_clocks()
188 reset_set_enable(PERIPH_ID_CORESIGHT, 0); in tegra124_init_clocks()
189 reset_set_enable(PERIPH_ID_MSELECT, 0); in tegra124_init_clocks()
190 reset_set_enable(PERIPH_ID_DVFS, 0); in tegra124_init_clocks()