Lines Matching refs:reset_set_enable
169 reset_set_enable(PERIPH_ID_CACHE2, 0); in t114_init_clocks()
170 reset_set_enable(PERIPH_ID_GPIO, 0); in t114_init_clocks()
171 reset_set_enable(PERIPH_ID_TMR, 0); in t114_init_clocks()
172 reset_set_enable(PERIPH_ID_COP, 0); in t114_init_clocks()
173 reset_set_enable(PERIPH_ID_EMC, 0); in t114_init_clocks()
174 reset_set_enable(PERIPH_ID_I2C5, 0); in t114_init_clocks()
175 reset_set_enable(PERIPH_ID_FUSE, 0); in t114_init_clocks()
176 reset_set_enable(PERIPH_ID_APBDMA, 0); in t114_init_clocks()
177 reset_set_enable(PERIPH_ID_MEM, 0); in t114_init_clocks()
178 reset_set_enable(PERIPH_ID_CORESIGHT, 0); in t114_init_clocks()
179 reset_set_enable(PERIPH_ID_MSELECT, 0); in t114_init_clocks()
180 reset_set_enable(PERIPH_ID_EMC1, 0); in t114_init_clocks()
181 reset_set_enable(PERIPH_ID_MC1, 0); in t114_init_clocks()
182 reset_set_enable(PERIPH_ID_DVFS, 0); in t114_init_clocks()