Lines Matching refs:mctl_ctl
21 struct sunxi_mctl_ctl_reg * const mctl_ctl = in mctl_phy_init() local
24 writel(val | PIR_INIT, &mctl_ctl->pir); in mctl_phy_init()
25 mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1); in mctl_phy_init()
30 struct sunxi_mctl_ctl_reg * const mctl_ctl = in mctl_set_bit_delays() local
34 clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26); in mctl_set_bit_delays()
40 &mctl_ctl->dx[i].bdlr[j]); in mctl_set_bit_delays()
44 &mctl_ctl->acbdlr[i]); in mctl_set_bit_delays()
49 writel(0x6 << 24, &mctl_ctl->dx[i].sdlr); in mctl_set_bit_delays()
52 setbits_le32(&mctl_ctl->pgcr[0], 1 << 26); in mctl_set_bit_delays()
270 struct sunxi_mctl_ctl_reg * const mctl_ctl = in mctl_h3_zq_calibration_quirk() local
284 clrsetbits_le32(&mctl_ctl->zqcr, 0xffff, in mctl_h3_zq_calibration_quirk()
287 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
290 reg_val = readl(&mctl_ctl->zqdr[0]); in mctl_h3_zq_calibration_quirk()
293 writel(reg_val, &mctl_ctl->zqdr[0]); in mctl_h3_zq_calibration_quirk()
295 reg_val = readl(&mctl_ctl->zqdr[1]); in mctl_h3_zq_calibration_quirk()
298 writel(reg_val, &mctl_ctl->zqdr[1]); in mctl_h3_zq_calibration_quirk()
299 writel(reg_val, &mctl_ctl->zqdr[2]); in mctl_h3_zq_calibration_quirk()
305 writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); in mctl_h3_zq_calibration_quirk()
312 &mctl_ctl->zqcr); in mctl_h3_zq_calibration_quirk()
314 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
317 zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff; in mctl_h3_zq_calibration_quirk()
318 writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]); in mctl_h3_zq_calibration_quirk()
320 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
323 val = readl(&mctl_ctl->zqdr[0]) >> 24; in mctl_h3_zq_calibration_quirk()
327 writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); in mctl_h3_zq_calibration_quirk()
328 writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); in mctl_h3_zq_calibration_quirk()
331 &mctl_ctl->zqdr[2]); in mctl_h3_zq_calibration_quirk()
369 struct sunxi_mctl_ctl_reg * const mctl_ctl = in mctl_sys_init() local
411 writel(socid == SOCID_H5 ? 0x8000 : 0xc00e, &mctl_ctl->clken); in mctl_sys_init()
424 struct sunxi_mctl_ctl_reg * const mctl_ctl = in mctl_channel_init() local
434 clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f); in mctl_channel_init()
436 setbits_le32(&mctl_ctl->pgcr[1], (1 << 24) | (1 << 26)); in mctl_channel_init()
438 clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26); in mctl_channel_init()
443 clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16); in mctl_channel_init()
458 clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask); in mctl_channel_init()
462 clrsetbits_le32(&mctl_ctl->aciocr, socid == SOCID_H5 ? (0x1 << 11) : 0, in mctl_channel_init()
466 setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6); in mctl_channel_init()
470 clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12)); in mctl_channel_init()
473 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), in mctl_channel_init()
477 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), in mctl_channel_init()
481 clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12)); in mctl_channel_init()
484 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), in mctl_channel_init()
491 writel(0x0, &mctl_ctl->dx[2].gcr); in mctl_channel_init()
492 writel(0x0, &mctl_ctl->dx[3].gcr); in mctl_channel_init()
494 writel(0x0, &mctl_ctl->dx[1].gcr); in mctl_channel_init()
501 clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, in mctl_channel_init()
513 clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ); in mctl_channel_init()
519 clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ); in mctl_channel_init()
526 if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) { in mctl_channel_init()
528 if (((readl(&mctl_ctl->dx[0].gsr[0]) >> 24) & 0x2) in mctl_channel_init()
530 || ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x2) in mctl_channel_init()
533 clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24); in mctl_channel_init()
539 if (((readl(&mctl_ctl->dx[2].gsr[0]) >> 24) & 0x1) || in mctl_channel_init()
540 ((readl(&mctl_ctl->dx[3].gsr[0]) >> 24) & 0x1)) { in mctl_channel_init()
541 writel(0x0, &mctl_ctl->dx[2].gcr); in mctl_channel_init()
542 writel(0x0, &mctl_ctl->dx[3].gcr); in mctl_channel_init()
546 if ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x1) { in mctl_channel_init()
547 writel(0x0, &mctl_ctl->dx[1].gcr); in mctl_channel_init()
557 if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) in mctl_channel_init()
562 mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1); in mctl_channel_init()
565 setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31); in mctl_channel_init()
567 clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31); in mctl_channel_init()
572 writel(0x00aa0060, &mctl_ctl->pgcr[3]); in mctl_channel_init()
574 writel(0xc0aa0060, &mctl_ctl->pgcr[3]); in mctl_channel_init()
577 setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN); in mctl_channel_init()
689 struct sunxi_mctl_ctl_reg * const mctl_ctl = in sunxi_dram_init() local
742 writel(0x00000303, &mctl_ctl->odtmap); in sunxi_dram_init()
744 writel(0x00000201, &mctl_ctl->odtmap); in sunxi_dram_init()
749 writel(0x0c000400, &mctl_ctl->odtcfg); in sunxi_dram_init()
753 setbits_le32(&mctl_ctl->vtfcr, in sunxi_dram_init()
756 clrbits_le32(&mctl_ctl->pgcr[2], (1 << 13)); in sunxi_dram_init()