88 	struct sunxi_mctl_ctl_reg * const mctl_ctl =  in auto_set_timing_para()  local
135 		writel(MCTL_MR0, &mctl_ctl->mr0);  in auto_set_timing_para()
136 		writel(MCTL_MR1, &mctl_ctl->mr1);  in auto_set_timing_para()
137 		writel(MCTL_MR2, &mctl_ctl->mr2);  in auto_set_timing_para()
138 		writel(MCTL_MR3, &mctl_ctl->mr3);  in auto_set_timing_para()
140 		writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0);  in auto_set_timing_para()
141 		writel(MCTL_LPDDR3_MR1, &mctl_ctl->mr1);  in auto_set_timing_para()
142 		writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2);  in auto_set_timing_para()
143 		writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr3);  in auto_set_timing_para()
172 	writel(reg_val, &mctl_ctl->dramtmg0);  in auto_set_timing_para()
174 	writel(reg_val, &mctl_ctl->dramtmg1);  in auto_set_timing_para()
176 	writel(reg_val, &mctl_ctl->dramtmg2);  in auto_set_timing_para()
178 	writel(reg_val, &mctl_ctl->dramtmg3);  in auto_set_timing_para()
180 	writel(reg_val, &mctl_ctl->dramtmg4);  in auto_set_timing_para()
182 	writel(reg_val, &mctl_ctl->dramtmg5);  in auto_set_timing_para()
184 	reg_val = readl(&mctl_ctl->dramtmg8);  in auto_set_timing_para()
189 	writel(reg_val, &mctl_ctl->dramtmg8);  in auto_set_timing_para()
194 	writel(reg_val, &mctl_ctl->pitmg0);  in auto_set_timing_para()
196 	writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);  in auto_set_timing_para()
197 	writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);  in auto_set_timing_para()
200 	writel(reg_val, &mctl_ctl->rfshtmg);  in auto_set_timing_para()
205 	struct sunxi_mctl_ctl_reg * const mctl_ctl =  in mctl_set_pir()  local
208 	writel(val, &mctl_ctl->pir);  in mctl_set_pir()
209 	mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);  in mctl_set_pir()
214 	struct sunxi_mctl_ctl_reg * const mctl_ctl =  in mctl_data_train_cfg()  local
218 		clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);  in mctl_data_train_cfg()
220 		clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);  in mctl_data_train_cfg()
225 	struct sunxi_mctl_ctl_reg * const mctl_ctl =  in mctl_train_dram()  local
231 	return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;  in mctl_train_dram()
260 	struct sunxi_mctl_ctl_reg * const mctl_ctl =  in mctl_channel_init()  local
278 	clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0 | 0x1 << 30);  in mctl_channel_init()
279 	clrsetbits_le32(&mctl_ctl->pgcr1, 0x1 << 24, 0x1 << 26);  in mctl_channel_init()
310 		setbits_le32(&mctl_ctl->pllgcr, 0x1 << 19);  in mctl_channel_init()
312 		setbits_le32(&mctl_ctl->pllgcr, 0x3 << 19);  in mctl_channel_init()
321 	clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));  in mctl_channel_init()
322 	clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));  in mctl_channel_init()
325 		clrsetbits_le32(&mctl_ctl->dxccr, (0x1 << 27) | (0x3<<6) ,  in mctl_channel_init()
328 		writel(0x00000303, &mctl_ctl->odtmap);  in mctl_channel_init()
330 		writel(0x00000201, &mctl_ctl->odtmap);  in mctl_channel_init()
376 	mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);  in mctl_channel_init()
379 	setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);  in mctl_channel_init()
382 	writel(0x00aa0060, &mctl_ctl->pgcr3);  in mctl_channel_init()
393 	struct sunxi_mctl_ctl_reg * const mctl_ctl =  in mctl_sys_init()  local
421 	writel(0x0000e00f, &mctl_ctl->clken);	/* normal */  in mctl_sys_init()
430 	struct sunxi_mctl_ctl_reg * const mctl_ctl =  in sunxi_dram_init()  local
466 		writel(0x00000303, &mctl_ctl->odtmap);  in sunxi_dram_init()
468 		writel(0x00000201, &mctl_ctl->odtmap);  in sunxi_dram_init()