89 	struct sunxi_mctl_ctl_reg * const mctl_ctl =  in auto_set_timing_para()  local
134 	writel(MCTL_MR0, &mctl_ctl->mr0);  in auto_set_timing_para()
135 	writel(MCTL_MR1, &mctl_ctl->mr1);  in auto_set_timing_para()
136 	writel(MCTL_MR2, &mctl_ctl->mr2);  in auto_set_timing_para()
137 	writel(MCTL_MR3, &mctl_ctl->mr3);  in auto_set_timing_para()
140 	writel(reg_val, &mctl_ctl->dramtmg0);  in auto_set_timing_para()
142 	writel(reg_val, &mctl_ctl->dramtmg1);  in auto_set_timing_para()
144 	writel(reg_val, &mctl_ctl->dramtmg2);  in auto_set_timing_para()
146 	writel(reg_val, &mctl_ctl->dramtmg3);  in auto_set_timing_para()
148 	writel(reg_val, &mctl_ctl->dramtmg4);  in auto_set_timing_para()
150 	writel(reg_val, &mctl_ctl->dramtmg5);  in auto_set_timing_para()
152 	reg_val = readl(&mctl_ctl->dramtmg8);  in auto_set_timing_para()
157 	writel(reg_val, &mctl_ctl->dramtmg8);  in auto_set_timing_para()
162 	writel(reg_val, &mctl_ctl->pitmg0);  in auto_set_timing_para()
164 	writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);  in auto_set_timing_para()
165 	writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);  in auto_set_timing_para()
168 	writel(reg_val, &mctl_ctl->rfshtmg);  in auto_set_timing_para()
173 	struct sunxi_mctl_ctl_reg * const mctl_ctl =  in mctl_set_pir()  local
176 	writel(val, &mctl_ctl->pir);  in mctl_set_pir()
177 	mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);  in mctl_set_pir()
182 	struct sunxi_mctl_ctl_reg * const mctl_ctl =  in mctl_data_train_cfg()  local
186 		clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);  in mctl_data_train_cfg()
188 		clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);  in mctl_data_train_cfg()
193 	struct sunxi_mctl_ctl_reg * const mctl_ctl =  in mctl_train_dram()  local
199 	return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;  in mctl_train_dram()
204 	struct sunxi_mctl_ctl_reg * const mctl_ctl =  in mctl_channel_init()  local
214 	clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0);  in mctl_channel_init()
227 		setbits_le32(&mctl_ctl->pllgcr, 0x1 << 18);  in mctl_channel_init()
229 		setbits_le32(&mctl_ctl->pllgcr, 0x3 << 18);  in mctl_channel_init()
238 	clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));  in mctl_channel_init()
239 	clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));  in mctl_channel_init()
244 	writel(CONFIG_DRAM_ZQ & 0xff, &mctl_ctl->zqcr1);  in mctl_channel_init()
248 	writel(readl(&mctl_ctl->zqsr0) | 0x10000000, &mctl_ctl->zqcr2);  in mctl_channel_init()
249 	writel((CONFIG_DRAM_ZQ >> 8) & 0xff, &mctl_ctl->zqcr1);  in mctl_channel_init()
284 	mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);  in mctl_channel_init()
287 	setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);  in mctl_channel_init()
299 	struct sunxi_mctl_ctl_reg * const mctl_ctl =  in mctl_sys_init()  local
322 	writel(0x0f802f01, &mctl_ctl->sched);  in mctl_sys_init()
323 	writel(0x0000400f, &mctl_ctl->clken);	/* normal */  in mctl_sys_init()
332 	struct sunxi_mctl_ctl_reg * const mctl_ctl =  in sunxi_dram_init()  local
356 		writel(0x00000303, &mctl_ctl->odtmap);  in sunxi_dram_init()
358 		writel(0x00000201, &mctl_ctl->odtmap);  in sunxi_dram_init()