19 static const struct socfpga_reset_manager *reset_manager_base =  variable
132 	setbits_le32(&reset_manager_base->per1modrst,  in socfpga_watchdog_disable()
139 	clrbits_le32(&reset_manager_base->brgmodrst,  in socfpga_reset_deassert_noc_ddr_scheduler()
148 	val = readl(&reset_manager_base->per1modrst);  in socfpga_is_wdt_in_reset()
184 		setbits_le32(&reset_manager_base->per0modrst, eccmask);  in socfpga_emac_manage_reset()
185 		setbits_le32(&reset_manager_base->per0modrst, emacmask);  in socfpga_emac_manage_reset()
188 		clrbits_le32(&reset_manager_base->per0modrst, emacmask);  in socfpga_emac_manage_reset()
189 		clrbits_le32(&reset_manager_base->per0modrst, eccmask);  in socfpga_emac_manage_reset()
222 	clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);  in socfpga_reset_deassert_bridges_handoff()
244 	setbits_le32(&reset_manager_base->per0modrst, mask0 & ECC_MASK);  in socfpga_reset_assert_fpga_connected_peripherals()
245 	setbits_le32(&reset_manager_base->per1modrst, mask1);  in socfpga_reset_assert_fpga_connected_peripherals()
246 	setbits_le32(&reset_manager_base->per0modrst, mask0);  in socfpga_reset_assert_fpga_connected_peripherals()
252 	clrbits_le32(&reset_manager_base->per1modrst,  in socfpga_reset_deassert_osc1wd0()
266 		reg = &reset_manager_base->mpumodrst;  in socfpga_per_reset()
269 		reg = &reset_manager_base->per0modrst;  in socfpga_per_reset()
272 		reg = &reset_manager_base->per1modrst;  in socfpga_per_reset()
275 		reg = &reset_manager_base->brgmodrst;  in socfpga_per_reset()
278 		reg = &reset_manager_base->sysmodrst;  in socfpga_per_reset()
313 	writel(~l4wd0, &reset_manager_base->per1modrst);  in socfpga_per_reset_all()
314 	setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);  in socfpga_per_reset_all()
317 	setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);  in socfpga_per_reset_all()
370 	setbits_le32(&reset_manager_base->brgmodrst,  in socfpga_bridges_reset()