Lines Matching refs:freeze_controller_base
16 static const struct socfpga_freeze_controller *freeze_controller_base = variable
36 writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); in sys_mgr_frzctrl_freeze_req()
41 &freeze_controller_base->vioctrl + channel_id); in sys_mgr_frzctrl_freeze_req()
76 clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); in sys_mgr_frzctrl_freeze_req()
83 reg_value = readl(&freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
91 writel(reg_value, &freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
97 reg_value = readl(&freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
102 writel(reg_value, &freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
118 writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); in sys_mgr_frzctrl_thaw_req()
123 = (u32)(&freeze_controller_base->vioctrl + channel_id); in sys_mgr_frzctrl_thaw_req()
156 clrbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
163 setbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
174 reg_value = readl(&freeze_controller_base->hioctrl); in sys_mgr_frzctrl_thaw_req()
179 writel(reg_value, &freeze_controller_base->hioctrl); in sys_mgr_frzctrl_thaw_req()
193 setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); in sys_mgr_frzctrl_thaw_req()
199 clrbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
206 setbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()