Lines Matching refs:sdr_pll
96 writel(0, &clock_manager_base->sdr_pll.en); in cm_basic_init()
114 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
131 readl(&clock_manager_base->sdr_pll.vco); in cm_basic_init()
140 writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); in cm_basic_init()
203 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
221 &clock_manager_base->sdr_pll.ddrdqsclk); in cm_basic_init()
224 &clock_manager_base->sdr_pll.ddr2xdqsclk); in cm_basic_init()
227 &clock_manager_base->sdr_pll.ddrdqclk); in cm_basic_init()
230 &clock_manager_base->sdr_pll.s2fuser2clk); in cm_basic_init()
251 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
263 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
270 (u32)&clock_manager_base->sdr_pll.ddrdqsclk, in cm_basic_init()
277 (u32)&clock_manager_base->sdr_pll.ddr2xdqsclk, in cm_basic_init()
283 (u32)&clock_manager_base->sdr_pll.ddrdqclk, in cm_basic_init()
289 (u32)&clock_manager_base->sdr_pll.s2fuser2clk, in cm_basic_init()
310 writel(~0, &clock_manager_base->sdr_pll.en); in cm_basic_init()
379 reg = readl(&clock_manager_base->sdr_pll.vco); in cm_get_sdram_clk_hz()
390 reg = readl(&clock_manager_base->sdr_pll.vco); in cm_get_sdram_clk_hz()
397 reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); in cm_get_sdram_clk_hz()