94 		&clock_manager_base->main_pll.en);  in cm_basic_init()
108 	       &clock_manager_base->main_pll.vco);  in cm_basic_init()
126 	       &clock_manager_base->main_pll.l4src);  in cm_basic_init()
129 	readl(&clock_manager_base->main_pll.vco);  in cm_basic_init()
138 	writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);  in cm_basic_init()
149 	writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);  in cm_basic_init()
155 	writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);  in cm_basic_init()
158 	writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);  in cm_basic_init()
162 	       &clock_manager_base->main_pll.cfgs2fuser0clk);  in cm_basic_init()
171 	writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);  in cm_basic_init()
177 	       &clock_manager_base->main_pll.mainnandsdmmcclk);  in cm_basic_init()
195 	       &clock_manager_base->main_pll.vco);  in cm_basic_init()
206 	writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);  in cm_basic_init()
208 	writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);  in cm_basic_init()
210 	writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);  in cm_basic_init()
236 	u32 mainvco = readl(&clock_manager_base->main_pll.vco);  in cm_basic_init()
240 	       &clock_manager_base->main_pll.vco);  in cm_basic_init()
255 	       &clock_manager_base->main_pll.vco);  in cm_basic_init()
305 	writel(cfg->l4src, &clock_manager_base->main_pll.l4src);  in cm_basic_init()
308 	writel(~0, &clock_manager_base->main_pll.en);  in cm_basic_init()
325 	reg = readl(&clock_manager_base->main_pll.vco);  in cm_get_main_vco_clk_hz()
369 	reg = readl(&clock_manager_base->main_pll.mpuclk);  in cm_get_mpu_clk_hz()
410 	reg = readl(&clock_manager_base->main_pll.l4src);  in cm_get_l4_sp_clk_hz()
420 		reg = readl(&clock_manager_base->main_pll.mainclk);  in cm_get_l4_sp_clk_hz()
431 	reg = readl(&clock_manager_base->main_pll.maindiv);  in cm_get_l4_sp_clk_hz()
454 		reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);  in cm_get_mmc_controller_clk_hz()
484 		reg = readl(&clock_manager_base->main_pll.mainqspiclk);  in cm_get_qspi_controller_clk_hz()