Lines Matching refs:clock_manager_base
14 static const struct socfpga_clock_manager *clock_manager_base = variable
23 writel(val, &clock_manager_base->bypass); in cm_write_bypass()
30 writel(val, &clock_manager_base->ctrl); in cm_write_ctrl()
84 readl(&clock_manager_base->per_pll.en), in cm_basic_init()
85 &clock_manager_base->per_pll.en); in cm_basic_init()
94 &clock_manager_base->main_pll.en); in cm_basic_init()
96 writel(0, &clock_manager_base->sdr_pll.en); in cm_basic_init()
99 writel(0, &clock_manager_base->per_pll.en); in cm_basic_init()
108 &clock_manager_base->main_pll.vco); in cm_basic_init()
111 &clock_manager_base->per_pll.vco); in cm_basic_init()
114 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
124 &clock_manager_base->per_pll.src); in cm_basic_init()
126 &clock_manager_base->main_pll.l4src); in cm_basic_init()
129 readl(&clock_manager_base->main_pll.vco); in cm_basic_init()
130 readl(&clock_manager_base->per_pll.vco); in cm_basic_init()
131 readl(&clock_manager_base->sdr_pll.vco); in cm_basic_init()
138 writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco); in cm_basic_init()
139 writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); in cm_basic_init()
140 writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); in cm_basic_init()
149 writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); in cm_basic_init()
152 writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk); in cm_basic_init()
155 writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk); in cm_basic_init()
158 writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk); in cm_basic_init()
162 &clock_manager_base->main_pll.cfgs2fuser0clk); in cm_basic_init()
165 writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk); in cm_basic_init()
168 writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk); in cm_basic_init()
171 writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk); in cm_basic_init()
173 writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk); in cm_basic_init()
177 &clock_manager_base->main_pll.mainnandsdmmcclk); in cm_basic_init()
180 &clock_manager_base->per_pll.pernandsdmmcclk); in cm_basic_init()
183 writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk); in cm_basic_init()
186 writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk); in cm_basic_init()
195 &clock_manager_base->main_pll.vco); in cm_basic_init()
199 &clock_manager_base->per_pll.vco); in cm_basic_init()
203 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
206 writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv); in cm_basic_init()
208 writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv); in cm_basic_init()
210 writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv); in cm_basic_init()
213 writel(cfg->perdiv, &clock_manager_base->per_pll.div); in cm_basic_init()
215 writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv); in cm_basic_init()
221 &clock_manager_base->sdr_pll.ddrdqsclk); in cm_basic_init()
224 &clock_manager_base->sdr_pll.ddr2xdqsclk); in cm_basic_init()
227 &clock_manager_base->sdr_pll.ddrdqclk); in cm_basic_init()
230 &clock_manager_base->sdr_pll.s2fuser2clk); in cm_basic_init()
236 u32 mainvco = readl(&clock_manager_base->main_pll.vco); in cm_basic_init()
240 &clock_manager_base->main_pll.vco); in cm_basic_init()
242 u32 periphvco = readl(&clock_manager_base->per_pll.vco); in cm_basic_init()
246 &clock_manager_base->per_pll.vco); in cm_basic_init()
251 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
255 &clock_manager_base->main_pll.vco); in cm_basic_init()
259 &clock_manager_base->per_pll.vco); in cm_basic_init()
263 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
270 (u32)&clock_manager_base->sdr_pll.ddrdqsclk, in cm_basic_init()
277 (u32)&clock_manager_base->sdr_pll.ddr2xdqsclk, in cm_basic_init()
283 (u32)&clock_manager_base->sdr_pll.ddrdqclk, in cm_basic_init()
289 (u32)&clock_manager_base->sdr_pll.s2fuser2clk, in cm_basic_init()
298 cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE); in cm_basic_init()
304 writel(cfg->persrc, &clock_manager_base->per_pll.src); in cm_basic_init()
305 writel(cfg->l4src, &clock_manager_base->main_pll.l4src); in cm_basic_init()
308 writel(~0, &clock_manager_base->main_pll.en); in cm_basic_init()
309 writel(~0, &clock_manager_base->per_pll.en); in cm_basic_init()
310 writel(~0, &clock_manager_base->sdr_pll.en); in cm_basic_init()
315 &clock_manager_base->inter); in cm_basic_init()
325 reg = readl(&clock_manager_base->main_pll.vco); in cm_get_main_vco_clk_hz()
340 reg = readl(&clock_manager_base->per_pll.vco); in cm_get_per_vco_clk_hz()
351 reg = readl(&clock_manager_base->per_pll.vco); in cm_get_per_vco_clk_hz()
367 reg = readl(&clock_manager_base->altera.mpuclk); in cm_get_mpu_clk_hz()
369 reg = readl(&clock_manager_base->main_pll.mpuclk); in cm_get_mpu_clk_hz()
379 reg = readl(&clock_manager_base->sdr_pll.vco); in cm_get_sdram_clk_hz()
390 reg = readl(&clock_manager_base->sdr_pll.vco); in cm_get_sdram_clk_hz()
397 reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); in cm_get_sdram_clk_hz()
410 reg = readl(&clock_manager_base->main_pll.l4src); in cm_get_l4_sp_clk_hz()
418 reg = readl(&clock_manager_base->altera.mainclk); in cm_get_l4_sp_clk_hz()
420 reg = readl(&clock_manager_base->main_pll.mainclk); in cm_get_l4_sp_clk_hz()
426 reg = readl(&clock_manager_base->per_pll.perbaseclk); in cm_get_l4_sp_clk_hz()
431 reg = readl(&clock_manager_base->main_pll.maindiv); in cm_get_l4_sp_clk_hz()
444 reg = readl(&clock_manager_base->per_pll.src); in cm_get_mmc_controller_clk_hz()
454 reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk); in cm_get_mmc_controller_clk_hz()
460 reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk); in cm_get_mmc_controller_clk_hz()
474 reg = readl(&clock_manager_base->per_pll.src); in cm_get_qspi_controller_clk_hz()
484 reg = readl(&clock_manager_base->main_pll.mainqspiclk); in cm_get_qspi_controller_clk_hz()
490 reg = readl(&clock_manager_base->per_pll.perqspiclk); in cm_get_qspi_controller_clk_hz()
504 reg = readl(&clock_manager_base->per_pll.perbaseclk); in cm_get_spi_controller_clk_hz()