511 			&clock_manager_base->per_pll.vco1);  in cm_pll_ramp_periph()
516 		per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1);  in cm_pll_ramp_periph()
571 	writel(0, &clock_manager_base->per_pll.en);  in cm_full_cfg()
577 	       &clock_manager_base->per_pll.bypasss);  in cm_full_cfg()
592 	       &clock_manager_base->per_pll.vco0);  in cm_full_cfg()
595 	writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1);  in cm_full_cfg()
640 			&clock_manager_base->per_pll.vco1);  in cm_full_cfg()
644 			&clock_manager_base->per_pll.vco1);  in cm_full_cfg()
653 	clrbits_le32(&clock_manager_base->per_pll.vco0,  in cm_full_cfg()
665 	writel((readl(&clock_manager_base->per_pll.vco0) &  in cm_full_cfg()
668 		&clock_manager_base->per_pll.vco0);  in cm_full_cfg()
704 	       &clock_manager_base->per_pll.cntr2clk);  in cm_full_cfg()
708 	       &clock_manager_base->per_pll.cntr3clk);  in cm_full_cfg()
712 	       &clock_manager_base->per_pll.cntr4clk);  in cm_full_cfg()
716 	       &clock_manager_base->per_pll.cntr5clk);  in cm_full_cfg()
720 	       &clock_manager_base->per_pll.cntr6clk);  in cm_full_cfg()
722 	writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk);  in cm_full_cfg()
726 	       &clock_manager_base->per_pll.cntr8clk);  in cm_full_cfg()
728 	writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk);  in cm_full_cfg()
754 	       &clock_manager_base->per_pll.gpiodiv);  in cm_full_cfg()
763 	       &clock_manager_base->per_pll.emacctl);  in cm_full_cfg()
776 	setbits_le32(&clock_manager_base->per_pll.vco0,  in cm_full_cfg()
782 	clrbits_le32(&clock_manager_base->per_pll.vco0,  in cm_full_cfg()
794 	       &clock_manager_base->per_pll.bypassr);  in cm_full_cfg()
814 	writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens);  in cm_full_cfg()
958 	clk_src = readl(&clock_manager_base->per_pll.vco0);  in cm_get_per_vco_clk_hz()
978 	vco = readl(&clock_manager_base->per_pll.vco1);  in cm_get_per_vco_clk_hz()
1036 	clk_input = readl(&clock_manager_base->per_pll.cntr6clk);  in cm_get_mmc_controller_clk_hz()
1049 		clk_hz /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &  in cm_get_mmc_controller_clk_hz()