481 			&clock_manager_base->main_pll.vco1);  in cm_pll_ramp_main()
486 		main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1);  in cm_pll_ramp_main()
568 		&clock_manager_base->main_pll.enr);  in cm_full_cfg()
575 	       &clock_manager_base->main_pll.bypasss);  in cm_full_cfg()
587 	       &clock_manager_base->main_pll.vco0);  in cm_full_cfg()
594 	writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1);  in cm_full_cfg()
620 			&clock_manager_base->main_pll.vco1);  in cm_full_cfg()
624 			&clock_manager_base->main_pll.vco1);  in cm_full_cfg()
650 	clrbits_le32(&clock_manager_base->main_pll.vco0,  in cm_full_cfg()
661 	writel((readl(&clock_manager_base->main_pll.vco0) &  in cm_full_cfg()
664 		&clock_manager_base->main_pll.vco0);  in cm_full_cfg()
677 	writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk);  in cm_full_cfg()
679 	writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk);  in cm_full_cfg()
681 	writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk);  in cm_full_cfg()
683 	writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk);  in cm_full_cfg()
685 	writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk);  in cm_full_cfg()
689 	       &clock_manager_base->main_pll.cntr7clk);  in cm_full_cfg()
691 	writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk);  in cm_full_cfg()
695 	       &clock_manager_base->main_pll.cntr9clk);  in cm_full_cfg()
698 	       &clock_manager_base->main_pll.cntr15clk);  in cm_full_cfg()
734 	       &clock_manager_base->main_pll.mpuclk);  in cm_full_cfg()
738 	       &clock_manager_base->main_pll.nocclk);  in cm_full_cfg()
751 		&clock_manager_base->main_pll.nocdiv);  in cm_full_cfg()
773 	setbits_le32(&clock_manager_base->main_pll.vco0,  in cm_full_cfg()
779 	clrbits_le32(&clock_manager_base->main_pll.vco0,  in cm_full_cfg()
788 	       &clock_manager_base->main_pll.bypassr);  in cm_full_cfg()
813 		&clock_manager_base->main_pll.ens);  in cm_full_cfg()
839 	nocclk = readl(&clock_manager_base->main_pll.nocclk);  in cm_get_noc_clk_hz()
873 		((readl(&clock_manager_base->main_pll.nocdiv) >>  in cm_get_l4_noc_hz()
914 	mainmpuclk_reg = readl(&clock_manager_base->main_pll.mpuclk);  in cm_get_mpu_clk_hz()
971 		src_hz /= (readl(&clock_manager_base->main_pll.cntr15clk) &  in cm_get_per_vco_clk_hz()
996 	u32 clk_src = readl(&clock_manager_base->main_pll.vco0);  in cm_get_main_vco_clk_hz()
1012 	vco = readl(&clock_manager_base->main_pll.vco1);  in cm_get_main_vco_clk_hz()
1043 		clk_hz /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &  in cm_get_mmc_controller_clk_hz()