125 #define GPIO4_IOC_BASE			0xFF568000  macro
169 #define UART0_RX_M2_ADDR		(GPIO4_IOC_BASE)
173 #define UART0_TX_M2_ADDR		(GPIO4_IOC_BASE)
197 #define UART1_RX_M2_ADDR		(GPIO4_IOC_BASE + 0x4)
201 #define UART1_TX_M2_ADDR		(GPIO4_IOC_BASE + 0x4)
286 #define UART5_TX_M2_ADDR		(GPIO4_IOC_BASE + 0x54)
420 		writel(0xffff1111, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_L);  in board_set_iomux()
421 		writel(0xffff1111, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_H);  in board_set_iomux()
422 		writel(0x00ff0011, GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L);  in board_set_iomux()
426 		writel(0x0f000700, GPIO4_IOC_BASE + 0x0030);  in board_set_iomux()
427 		writel(0xff002200, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_L);  in board_set_iomux()
428 		writel(0x0f0f0202, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_H);  in board_set_iomux()
429 		writel(0x00ff0022, GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L);  in board_set_iomux()
466 	if ((readl(GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L) & 0x70) == 0x20)  in arch_cpu_init()
467 		writel(0x3f000700, GPIO4_IOC_BASE + GPIO4_IOC_GPIO4B_DS0);  in arch_cpu_init()
525 	writel(0x0f000700, GPIO4_IOC_BASE + 0x0030);  in arch_cpu_init()
526 	writel(0xff002200, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_L);  in arch_cpu_init()
527 	writel(0x0f0f0202, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_H);  in arch_cpu_init()
528 	writel(0x00ff0022, GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L);  in arch_cpu_init()
531 	writel(0xffff1111, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_L);  in arch_cpu_init()
532 	writel(0xffff1111, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_H);  in arch_cpu_init()
533 	writel(0x00ff0011, GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L);  in arch_cpu_init()
542 	writel(0x000c000c, GPIO4_IOC_BASE + GPIO4_IOC_SARADC_IO_CON);  in arch_cpu_init()