37 #define TOP_IOC_BASE		0x26044000  macro
200 			writel(0xffff1111, TOP_IOC_BASE + GPIO1A_IOMUX_SEL_L);  in board_set_iomux()
201 			writel(0xffff1111, TOP_IOC_BASE + GPIO1A_IOMUX_SEL_H);  in board_set_iomux()
202 			writel(0xffff1111, TOP_IOC_BASE + GPIO1B_IOMUX_SEL_L);  in board_set_iomux()
204 			writel(0xffff1111, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L);  in board_set_iomux()
205 			writel(0x00ff0011, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_H);  in board_set_iomux()
213 			writel(0xffff2222, TOP_IOC_BASE + GPIO1A_IOMUX_SEL_L);  in board_set_iomux()
214 			writel(0xffff2020, TOP_IOC_BASE + GPIO1B_IOMUX_SEL_L);  in board_set_iomux()
217 			writel(0xffff2222, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L);  in board_set_iomux()
218 			writel(0x00ff0022, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_H);  in board_set_iomux()
223 			writel(0xf0003000, TOP_IOC_BASE + GPIO1C_IOMUX_SEL_L);  in board_set_iomux()
224 			writel(0xffff3333, TOP_IOC_BASE + GPIO1C_IOMUX_SEL_H);  in board_set_iomux()
225 			writel(0x00f00030, TOP_IOC_BASE + GPIO1D_IOMUX_SEL_H);  in board_set_iomux()
241 			writel(0xffff0000, TOP_IOC_BASE + GPIO1A_IOMUX_SEL_L);  in board_unset_iomux()
242 			writel(0xffff0000, TOP_IOC_BASE + GPIO1B_IOMUX_SEL_L);  in board_unset_iomux()
245 			writel(0xffff0000, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L);  in board_unset_iomux()
246 			writel(0x00ff0000, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_H);  in board_unset_iomux()
249 			writel(0xf0000000, TOP_IOC_BASE + GPIO1C_IOMUX_SEL_L);  in board_unset_iomux()
250 			writel(0xffff0000, TOP_IOC_BASE + GPIO1C_IOMUX_SEL_H);  in board_unset_iomux()
251 			writel(0x00f00000, TOP_IOC_BASE + GPIO1D_IOMUX_SEL_H);  in board_unset_iomux()
414 	if (readl(TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L) != 0x2222)  in arch_cpu_init()